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PCMD3140 数据表(PDF) 21 Page - Texas Instruments |
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PCMD3140 数据表(HTML) 21 Page - Texas Instruments |
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21 / 111 page ![]() 1 0 N-1 N-1 N-2 1 0 Left Slot-0 (Word Length : N) Left Slot-2 to Slot-3 (Word Length : N) 1 0 N-1 BCLK SDOUT n th Sample (n+1) th Sample 1 0 N-1 N-1 1 0 Right Slot-0 (Word Length : N) Right Slot-2 to Slot-3 (Word Length : N) Left Slot-0 (Word Length : N) TX_OFFSET = 2 TX_OFFSET = 2 TX_OFFSET = 2 FSYNC Figure 7-10. LJ Protocol Timing (TX_OFFSET = 2) 1 0 N-1 N-2 N-1 N-2 0 N-1 Left Slot-1 to Slot-3 (Word Length : N) 1 0 N-1 N-2 BCLK SDOUT n th Sample (n+1) th Sample 1 0 N-1 0 N-1 1 0 Right Slot-1 to Slot-3 (Word Length : N) Left Slot-0 (Word Length : N) 1 0 0 N-1 N-2 FSYNC Figure 7-11. LJ Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0) 1 0 N-1 N-2 N-1 N-2 1 0 Left Slot-0 (Word Length : N) Left Slot-2 to Slot-3 (Word Length : N) 1 0 N-1 N-2 BCLK SDOUT n th Sample (n+1) th Sample 1 0 N-1 N-1 N-2 1 0 Right Slot-0 (Word Length : N) Right Slot-2 to Slot-3 (Word Length : N) Left Slot-0 (Word Length : N) FSYNC TX_OFFSET = 1 TX_OFFSET = 1 TX_OFFSET = 1 Figure 7-12. LJ Protocol Timing (TX_OFFSET = 1 and BCLK_POL = 1) For proper operation of the audio bus in LJ mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels (including left and right slots) times the programmed word length of the output channel data. The device FSYNC high pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC low pulse must be number of BCLK cycles wide that is greater than or equal to the number of active right slots times the data word length configured. For a higher BCLK frequency operation, using LJ mode with a TX_OFFSET value higher than 0 is recommended. www.ti.com PCMD3140-Q1 SBASAH3A – APRIL 2022 – REVISED SEPTEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: PCMD3140-Q1 |
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