6

ICS94236

0451A

—01/10/03

Byte 1: CPU, Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B

-

X#

2

S

F

6

t

i

B6

4

1K

L

C

U

P

C

5

t

i

B

-

1)

d

e

v

r

e

s

e

R

(

4

t

i

B

-

X#

3

S

F

3

t

i

B0

4

1T

U

O

_

M

A

R

D

S

2

t

i

B

-

X#

)

#

8

4

_

4

2

L

E

S

(

1

t

i

B4

4

,

3

41

h

t

o

b

(

e

l

b

a

n

e

0

K

L

C

U

P

C

d

n

a

"

e

u

r

T

"

.

r

i

a

p

l

a

i

t

n

e

r

e

f

f

i

d

)

"

y

r

a

t

n

e

m

i

l

p

m

o

C

0

t

i

B

-

1*

)

d

e

v

r

e

s

e

R

(

Byte 2: PCI, Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B

-

X#

0

S

F

6

t

i

B

7

1F

_

K

L

C

I

C

P

5

t

i

B

-

1)

d

e

v

r

e

s

e

R

(

4

t

i

B3

1

14

K

L

C

I

C

P

3

t

i

B2

1

13

K

L

C

I

C

P

2

t

i

B1

1

12

K

L

C

I

C

P

1

t

i

B0

1

11

K

L

C

I

C

P

0

t

i

B

8

10

K

L

C

I

C

P

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

2. Latched Frequency Selects (FS#) will be inverted logic

load of the input frequency select pin conditions.

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B8

2

17

M

A

R

D

S

6

t

i

B9

2

16

M

A

R

D

S

5

t

i

B1

3

15

M

A

R

D

S

4

t

i

B2

3

14

M

A

R

D

S

3

t

i

B4

3

13

M

A

R

D

S

2

t

i

B5

3

12

M

A

R

D

S

1

t

i

B7

3

11

M

A

R

D

S

0

t

i

B8

3

10

M

A

R

D

S

Byte 4: SDRAM , Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B

-

1)

d

e

v

r

e

s

e

R

(

6

t

i

B

-

1)

d

e

v

r

e

s

e

R

(

5

t

i

B

-

1)

d

e

v

r

e

s

e

R

(

4

t

i

B

-

Xe

d

o

M

3

t

i

B

-

X#

1

S

F

2

t

i

B

-

1)

d

e

v

r

e

s

e

R

(

1

t

i

B8

4

11

F

E

R

0

t

i

B

2

10

F

E

R

Byte 5: Peripheral , Active/Inactive Register

(1= enable, 0 = disable)

Byte 3: SDRAM, Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B

-

0)

e

t

o

N

(

d

e

v

r

e

s

e

R

6

t

i

B

-

0)

e

t

o

N

(

d

e

v

r

e

s

e

R

5

t

i

B

-

0)

e

t

o

N

(

d

e

v

r

e

s

e

R

4

t

i

B

-

0)

e

t

o

N

(

d

e

v

r

e

s

e

R

3

t

i

B

-

0)

e

t

o

N

(

d

e

v

r

e

s

e

R

2

t

i

B

-

1)

e

t

o

N

(

d

e

v

r

e

s

e

R

1

t

i

B

-

1)

e

t

o

N

(

d

e

v

r

e

s

e

R

0

t

i

B

-

0)

e

t

o

N

(

d

e

v

r

e

s

e

R

Byte 6: Peripheral , Active/Inactive Register

(1= enable, 0 = disable)

Note: Don

’t write into this register, writing into this

register can cause malfunction

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B

-

1)

d

e

v

r

e

s

e

R

(

6

t

i

B

-

1)

d

e

v

r

e

s

e

R

(

5

t

i

B6

2

1z

H

M

8

4

4

t

i

B5

2

1z

H

M

8

4

_

4

2

3

t

i

B7

1

11

1

M

A

R

D

S

2

t

i

B8

1

10

1

M

A

R

D

S

1

t

i

B0

2

19

M

A

R

D

S

0

t

i

B1

2

18

M

A

R

D

S

Note:

* It is recommended to drive this bit to 0.