MP4572

– 60V, 2A, SYNCHRONOUS STEP-DOWN CONVERTER

MP4572 Rev. 1.0

www.MonolithicPower.com

22

3/9/2020

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that is compatible with popular logic devices.

Positive logic indicates that when the input voltage

exceeds

the

under-voltage

lockout

(UVLO)

threshold (about 4.0V), the converter is enabled by

pulling the EN pin above 1.45V. Drive the EN pin

below 1.12V to disable the MP4572. An internal

resistor (REN) from EN to GND allows EN to be

floated to shut down the chip (REN = 2.8MΩ when

EN is on; REN = 1.8MΩ when EN is off).

SYNCO

The MP4572 has a SYNCO pin. During start-up,

SYNCO stays low and quickly outputs a 180°

phase-shift clock to the internal oscillator once

soft start is ready. Note that the falling edge of

SYNCO is a 180° phase-shift to the rising edge

of the internal oscillator. This function allows two

devices to operate in the same frequency, but 180°

out of phase, which reduces the total input current

ripple. This allows a smaller input bypass capacitor

to be used.

Internal Regulator

A 4.9V internal regulator powers most of the

internal circuitries. This regulator takes VIN and

operates in the full VIN range. When VIN exceeds

4.9V, the output of the regulator is in full

regulation. Lower VIN values result in lower output

voltages. The regulator is enabled when VIN

exceeds

its

under-voltage

lockout

(UVLO)

threshold and EN is high. In EN shutdown mode,

the internal VCC regulator is disabled to reduce

power dissipation.

Configurable Frequency and Foldback

The oscillating frequency (fSW) of the MP4572 is

configured by an external frequency resistor. The

frequency resistor should be located between

FREQ pin and GND, as close as possible to the

device. Select a proper RFREQ, calculated with

Equation (1):

(kHz)

f

30

M

R

SW

FREQ



)

Ω

(

(1)

The calculated resistance may need fine-tuning

with a bench test.

It is not possible to use a high fSW with a high VIN,

since the minimum on time required for the HS-

FET

is

limited.

The

MP4572

control

loop

automatically sets the maximum possible fSW up to

the set frequency, which also reduces excessive

power loss in the IC. VOUT is regulated by varying

the duration of the switch-off time of the HS-FET,

which results in an automatic reduction of fSW.

Compliance with the minimum on time of the HS-

FET is guaranteed. An advantage of this method is

that the device works at the desired fSW as long as

possible, and a correction is only made at high VIN.

For the Switching Frequency vs. VIN curve, see the

Typical Performance Characteristics section on

page 12, where RFREQ equals 12.1kΩ.

Internal Soft Start

To avoid overshoot during start-up, the MP4572

has built-in soft start (SS) that ramps up the

output voltage at a controlled slew rate when the

EN pin goes high. When the SS voltage (VSS) is

below the internal reference (VREF), VSS overrides

VREF as the error amplifier reference. When VSS

exceeds VREF, VREF acts as the reference. At this

point, soft start finishes and the MP4572 enters

steady-state.

The SS time is internally set to 0.45ms. When the

output voltage is shorted to GND, the feedback

voltage is pulled low and VSS is discharged. The

part initiates soft start again when it returns to a

normal state.

Pre-Biased Start-Up

If VFB exceeds VSS during start-up, that means

the output has a pre-biased voltage. Neither the

HS-FET nor LS-FET turns on until VSS exceeds

VFB. Note that the pre-biased capability is only

available when the device is set to AAM.

Power Good (PG) Indicator

The MP4572 has power good (PG) indication.

The PG pin is the open drain of a MOSFET. It

should be connected to a voltage source through

a resistor (e.g. 100k

Ω). In the presence of an

input voltage, the MOSFET turns on so that the

PG pin is pulled to GND before soft start is ready.

PG goes high if the output voltage is between

90% and 108% of the nominal voltage after a

70

μs delay. PG goes low when the output

voltage is above 116% or below 94% of the

nominal voltage after a 25

μs delay.

Under-Voltage Lockout Protection (UVLO)

The MP4572 has input under-voltage lockout

protection (UVLO) to ensure reliable output

power. Assuming EN is active, the MP4572 is

powered on when the input voltage exceeds the

UVLO rising threshold. The device is powered off