LT3041 datasheet(21/36 Pages) AD

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Data Sheet

LT3041

APPLICATIONS INFORMATION

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Rev. 0 | 21 of 36

The LT3041 is a high-performance, low-dropout, linear regulator

that features Analog Devices ultra-low noise (3 nV/√Hz at 10

kHz) and ultra-high PSRR (80 dB at 1 MHz) architecture for pow-

ering noise-sensitive applications. Designed as a precision-current

source followed by a high-performance, rail-to-rail voltage buffer,

the LT3041 can be easily paralleled to further reduce noise, in-

crease output current, and spread heat on the PCB. The LT3041

additionally features programmable current limit, a fast start-up

capability, and programmable power good.

The LT3041 is simple to use and incorporates all of the protection

features expected in high-performance regulators. Included are

short-circuit protection, safe-operating area protection, reverse-bat-

tery protection, reverse-current protection, and thermal shutdown

with hysteresis.

In addition to the LT3041 feature set, the LT3041 incorporates a

VIOC tracking function to control an upstream switching converter

to maintain a constant voltage across the LT3041 and, therefore, to

minimize power dissipation.

OUTPUT VOLTAGE

The LT3041 incorporates precision 100 μA current source flowing

out of the SET pin, which also connects to the inverting input of

the error amplifier. Figure 71 illustrates that connecting a resistor

from SET to ground generates a reference voltage for the error

amplifier. This reference voltage is the product of the SET pin

current and the SET pin resistor. The unity-gain configuration of the

error amplifier produces a low-impedance version of this voltage

on its noninverting input, that is, the OUTS pin, which is externally

connected to the OUT pin.

Figure 71. Basic Adjustable Regulator

The rail-to-rail error amplifier and current reference of the LT3041

allows for a wide output voltage range from 0.2 V to VIN minus

dropout, up to 15 V. A PNP-based input pair is active for a 0.2 V

to ~0.95 V output and an NPN-based input pair is active for output

voltages greater than ~0.95 V, with an abrupt transition between

the two input pairs at ~0.95 V output with approximately 24 mV

of hysteresis. While the NPN-based input pair is designed to offer

the best overall performance, refer to the Table 1 for details on the

offset voltage, SET pin current, output noise, and PSRR variation

with the error-amplifier input pair. Table 4 lists many common output

voltages and their corresponding 1% RSET resistors.

Table 4. 1% Resistor for Common Output Voltages

VOUT (V)

RSET (kΩ)

2.5

24.9

3.3

33.2

49.9

121

150

The benefit of using a current reference compared to the typical

voltage reference used in conventional regulators is that the regula-

tor always operates in a unity-gain configuration, independent of the

programmed output voltage. This configuration allows the LT3041

to have loop gain, frequency response, and bandwidth independent

of the output voltage. As a result, noise, PSRR, and transient

performance do not change with output voltage. Moreover, because

none of the error-amplifier gain is needed to amplify the SET pin

voltage to a higher output voltage, output load regulation is more

tightly specified in the hundreds of microvolts range and not as a

fixed percentage of the output voltage.

Because the zero temperature-coefficient current source is highly

accurate, the SET pin resistor can become a limiting factor in

achieving high accuracy. Therefore, the SET pin resistor must be

a precision resistor. Additionally, any leakage paths to or from the

SET pin create errors in the output voltage. If necessary, use high-

quality insulation (for example, Teflon or Kel-F). Moreover, cleaning

of all insulating surfaces to remove fluxes and other residues can

be required. High humidity environments can require a surface

coating at the SET pin to provide a moisture barrier.

Minimize board leakage by encircling the SET pin with a guard

ring that operates at a potential close to itself, ideally connected

to the OUT pins. Guarding both sides of the circuit board is recom-

mended. Bulk leakage reduction depends on the guard-ring width.

Leakages of 100 nA into or out of the SET pin creates a 0.1% error

in the reference voltage. Leakages of this magnitude, coupled with

other sources of leakage, can cause significant errors in the output

voltage, especially over a wide operating temperature range. Figure

72 illustrates a typical guard-ring layout technique.

Figure 72. DFN Guard Ring Layout

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