22

www.diodes.com

April 2019

Diodes Incorporated

PI7C9X752

Document Number DS40312 Rev 3-2

A product Line of

Diodes Incorporated

PI7C9X752

25000

48

20

0

38400

25

25

0

57600

22

19

0.32

115200

8

26

0.16

225000

6

18

1.2

400000

3

20

0

921600

1

26

0.16

1000000

1

24

0

10. RS-485 Features

10.1 Auto RS-485 RTS Control

Normally the RTS pin is controlled by MCR bit 1, or if hardware flow control is enabled, the logic state of the RTS pin is controlled

by the hardware flow control circuitry. DLD register bit 6 will take the precedence over the other two modes; once this bit is set, the

transmitter will control the state of the RTS pin. The transmitter automatically de-asserts the RTS pin (logic 1) once the host writes

data to the transmit FIFO, and asserts RTS pin (logic 0) once the last bit of the data has been transmitted.

To use the auto RS-485 RTS mode the software would have to disable the hardware flow control function.

10.2 RS-485 RTS Output Inversion

RS485 register bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode. When the transmitter has data to be

sent it asserts the RTS pin (logic 0), and when the last bit of the data has been sent out the transmitter de-asserts the RTS pin (logic 1).

10.3 Auto RS-485

RS485 register bit 0 is used to enable the RS-485 mode (multidrop or 9-bit mode). In this mode of operation, a ‘master’ station trans-

mits an address character followed by data characters for the addressed ‘slave’ stations. The slave stations examine the received data

and interrupt the controller if the received character is an address character (parity bit = 1).

To use the auto RS-485 RTS mode the software would have to disable the hardware flow control function.

10.3.1 Normal Multidrop Mode

The 9-bit mode in RS485 register bit 0 is enabled, but not Special Character Detect (EFR bit 5). The receiver is set to Force Parity 0

(LCR[5:3] = 111) in order to detect address bytes.

With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an address byte is received (parity bit = 1). This

address byte will cause the UART to set the parity error. The UART will generate a line status interrupt (IER bit 2 must be set to ‘1’ at

this time), and at the same time puts this address byte in the RX FIFO. After the controller examines the byte it must make a decision

whether or not to enable the receiver; it should enable the receiver if the address byte addresses its ID address, and must not enable the

receiver if the address byte does not address its ID address.

If the controller enables the receiver, the receiver will receive the subsequent data until being disabled by the controller after the

controller has received a complete message from the ‘master’ station. If the controller does not disable the receiver after receiving a

message from the ‘master’ station, the receiver will generate a parity error upon receiving another address byte. The controller then

determines if the address byte addresses its ID address, if it is not, the controller then can disable the receiver. If the address byte ad-

dresses the ‘slave’ ID address, the controller take no further action; the receiver will receive the subsequent data.