NAND512-B datasheet(21/59 Pages) STMICROELECTRONICS

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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B

Cache Read

The Cache Read operation is used to improve the

read throughput by reading data using the Cache

page, the device automatically loads the next page

into the Cache Register.

An Cache Read operation consists of three steps

(see Table 10.):

One bus cycle is required to setup the Cache

Read command (the same as the standard

Read command)

Four or Five (refer to Table 6. and Table 7.)

bus cycles are then required to input the Start

Address

One bus cycle is required to issue the Cache

Read confirm command to start the P/E/R

Controller.

The Start Address must be at the beginning of a

page (Column Address = 00h, see Table 8. and

Table 9.). This allows the data to be output unin-

terrupted after the latency time (tBLBH1), see Fig-

ure 11.

The Ready/Busy signal can be used to monitor the

start of the operation. During the latency period the

Ready/Busy signal goes Low, after this the Ready/

Busy signal goes High, even if the device is inter-

nally downloading page n+1.

Once the Cache Read operation has started, the

Status Register can be read using the Read Status

During the operation, SR5 can be read, to find out

whether the internal reading is ongoing (SR5 =

‘0’), or has completed (SR5 = ‘1’), while SR6 indi-

cates whether the Cache Register is ready to

download new data.

To exit the Cache Read operation an Exit Cache

Read command must be issued (see Table 10.).

If the Exit Cache Read command is issued while

the device is internally reading page n+1, page n

will still be output, but not page n+1.

Figure 11. Cache Read Operation

I/O

Address

Inputs

ai08661

00h

Read

Setup

Code

31h

Cache

Read

Confirm

Code

Busy

tBLBH1

(Read Busy time)

1st page

Data Output

2nd page

3rd page

last page

34h

Exit

Cache

Read

Code

Block N

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