NAND01G-B datasheet(28/59 Pages) STMICROELECTRONICS

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Read Status Register

The device contains a Status Register which pro-

vides information on the current or previous Pro-

gram or Erase operation. The various bits in the

Status Register convey information and errors on

the operation.

The Status Register is read by issuing the Read

Status Register command. The Status Register in-

formation is present on the output data bus (I/O0-

I/O7) on the falling edge of Chip Enable or Read

Enable, whichever occurs last. When several

memories are connected in a system, the use of

Chip Enable and Read Enable signals allows the

system to poll each device separately, even when

the Ready/Busy pins are common-wired. It is not

necessary to toggle the Chip Enable or Read En-

able signals to update the contents of the Status

After the Read Status Register command has

been issued, the device remains in Read Status

Therefore if a Read Status Register command is

issued during a Random Read cycle a new Read

command must be issued to continue with a Page

Read operation.

The Status Register bits are summarized in Table

13., Status Register Bits, . Refer to Table 13. in

conjunction with the following text descriptions.

Write Protection Bit (SR7). The Write Protection

bit can be used to identify if the device is protected

or not. If the Write Protection bit is set to ‘1’ the de-

vice is not protected and program or erase opera-

tions are allowed. If the Write Protection bit is set

to ‘0’ the device is protected and program or erase

operations are not allowed.

P/E/R Controller and Cache Ready/Busy Bit

(SR6). Status Register bit SR6 has two different

functions depending on the current operation.

During Cache Program operations SR6 acts as a

Cache Program Ready/Busy bit, which indicates

whether the Cache Register is ready to accept

new data. When SR6 is set to '0', the Cache Reg-

ister is busy and when SR6 is set to '1', the Cache

During all other operations SR6 acts as a P/E/R Con-

troller bit, which indicates whether the P/E/R Con-

troller is active or inactive. When the P/E/R

Controller bit is set to ‘0’, the P/E/R Controller is

active (device is busy); when the bit is set to ‘1’, the

P/E/R Controller is inactive (device is ready).

P/E/R Controller Bit (SR5). The Program/Erase/

Read Controller bit indicates whether the P/E/R

Controller is active or inactive. When the P/E/R

Controller bit is set to ‘0’, the P/E/R Controller is

active (device is busy); when the bit is set to ‘1’, the

P/E/R Controller is inactive (device is ready).

Cache Program Error Bit (SR1). The Cache Pro-

gram Error bit can be used to identify if the previous

page (page N-1) has been successfully pro-

gramed or not in a Cache Program operation. SR1

is set to ’1’ when the Cache Program operation

has failed to program the previous page (page N-

1) correctly. If SR1 is set to ‘0’ the operation has

completed successfully.

The Cache Program Error bit is only valid during

Cache Program operations, during other opera-

tions it is Don’t Care.

Error Bit (SR0). The Error bit is used to identify if

any errors have been detected by the P/E/R Con-

troller. The Error Bit is set to ’1’ when a program or

erase operation has failed to write the correct data

to the memory. If the Error Bit is set to ‘0’ the oper-

ation has completed successfully. The Error Bit

SR0, in a Cache Program operation, indicates a

failure on Page N.

SR4, SR3 and SR2 are Reserved.

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