STM32H753II datasheet(40/361 Pages) STMICROELECTRONICS

40 / 361 page

Functional overview

STM32H753xI

40/360

DS12117 Rev 8

3.28

Cryptographic acceleration (CRYP and HASH)

The devices embed a cryptographic processor that supports the advanced cryptographic

algorithms usually required to ensure confidentiality, authentication, data integrity and non-

repudiation when exchanging messages with a peer:

•

Encryption/Decryption

–

DES/TDES (data encryption standard/triple data encryption standard): ECB

(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,

128- or 192-bit key

–

AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (Counter

mode) chaining algorithms, 128, 192 or 256-bit key

•

Universal HASH

–

SHA-1 and SHA-2 (secure HASH algorithms)

–MD5

–HMAC

The cryptographic accelerator supports DMA request generation.

3.29

Timers and watchdogs

The devices include one high-resolution timer, two advanced-control timers, ten general-

purpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer.

All timer counters can be frozen in Debug mode.

Table 5 compares the features of the advanced-control, general-purpose and basic timers.

Table 5. Timer feature comparison

Timer

type

Timer

Counter

resolution

Counter

type

Prescaler

factor

DMA

request

generation

Capture/

compare

channels

Comple-

mentary

output

Max

interface

clock

(MHz)

Max

timer

clock

(MHz)

(1)

High-

resolution

timer

HRTIM1

16-bit

/1 /2 /4

(x2 x4 x8

x16 x32,

with DLL)

Yes

480

Advanced

-control

TIM1,

TIM8

16-bit

Up,

Down,

Up/down

Any

integer

between 1

and

65536

Yes

120

240

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