STM32W108HB datasheet(13/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

Description

Doc ID 16252 Rev 14

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The STM32W108 has an ultra low power, deep sleep state with a choice of clocking modes.

The sleep timer can be clocked with either the external 32.768 kHz crystal oscillator or with

a 1 kHz clock derived from the internal 10 kHz LSI RC oscillator. Alternatively, all clocks can

be disabled for the lowest power mode. In the lowest power mode, only external events on

GPIO pins will wake up the chip. The STM32W108 has a fast startup time (typically 100 µs)

from deep sleep to the execution of the first ARM® Cortex-M3 instruction.

The STM32W108 contains three power domains. The always-on high voltage supply powers

the GPIO pads and critical chip functions. Regulated low voltage supplies power the rest of

the chip. The low voltage supplies are be disabled during deep sleep to reduce power

consumption. Integrated voltage regulators generate regulated 1.25 V and 1.8 V voltages

from an unregulated supply voltage. The 1.8 V regulator output is decoupled and routed

externally to supply analog blocks, RAM, and Flash memories. The 1.25 V regulator output

is decoupled externally and supplies the core logic.

The digital section of the receiver uses a coherent demodulator to generate symbols for the

hardware-based MAC. The digital receiver also contains the analog radio calibration

routines and controls the gain within the receiver path.

In addition to 2 general-purpose timers, the STM32W108 also contains a watchdog timer to

ensure protection against software crashes and CPU lockup, a 32-bit sleep timer dedicated

to system timing and waking from sleep at specific times and an ARM® standard system

event timer in the NVIC.

The STM32W108 integrates hardware support for a Packet Trace module, which allows

robust packet-based debug.

Note:

The STM32W108 is not pin-compatible with the previous generation chip, the SN250,

except for the RF section of the chip. Pins 1-11 and 45-48 are compatible, to ease migration

to the STM32W108.

1.2.2

ARM® Cortex™-M3 core

The STM32W108 integrates the ARM® Cortex™-M3 microprocessor, revision r1p1,

developed by ARM Ltd, making the STM32W108 a true system-on-a-chip solution. The

ARM® Cortex-M3 is an advanced 32-bit modified Harvard architecture processor that has

separate internal program and data buses, but presents a unified program and data address

space to software. The word width is 32 bits for both the program and data sides. The

ARM® Cortex-M3 allows unaligned word and half-word data accesses to support efficiently-

packed data structures.

The ARM® Cortex-M3 clock speed is configurable to 6 MHz, 12 MHz, or 24 MHz. For

normal operation 12 MHz is preferred over 24 MHz due to its lower power consumption. The

6 MHz operation can only be used when radio operations are not required since the radio

requires an accurate 12 MHz clock.

The ARM® Cortex-M3 in the STM32W108 has also been enhanced to support two separate

memory protection levels. Basic protection is available without using the MPU, but the usual

operation uses the MPU. The MPU protects unimplemented areas of the memory map to

prevent common software bugs from interfering with software operation. The architecture

could also separate the networking stack from the application code using a fine granularity

RAM protection module. Errant writes are captured and details are reported to the developer

to assist in tracking down and fixing issues.

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