1.4 - 7.1 GHz Positive Gain Slope Amplifier +2dB

CMX90G302

www.cmlmicro.com

Page 14

D/90G302/3 September 2022

Thermal Design

The primary RF/DC ground and thermal path is via the exposed die pad on the backside of the package, which must be

connected to the PCB ground plane. An array of plated through-hole vias directly underneath the die pad area is

essential to conduct heat away and minimise ground inductance. A typical solution will have 9 grounding vias

connecting the top layer to the bottom layer, with inner diameter of 0.2 mm (and 0.025 mm plating) on 0.5 mm grid

pattern. The vias do not need to be filled. The PCB layout should provide a thermal radiator appropriate for the

intended operation, adding as much copper to inner and outer layers as possible to avoid excessive junction

temperature.

Device junction temperature (Tj) can be calculated using Tj = Tc + (Pdiss x Rjc) where Pdiss = Pdc + Pin – Pout and Tc is

the case temperature on the backside of the package (die pad) in contact with the PCB.

Ven Input

The device is enabled by applying a voltage between 1.8 V and 5.0 V to pin 16 (Ven). The resulting Id taken by the

device is relatively independent of the Ven voltage applied. If the enable feature is not required, the Ven pin can be

connected to the same voltage as Vd.

The device can be placed into standby mode when not in use by setting Ven low (<0.2V) to disable all circuitry.

If lower Ien and Id leakage current and/or if the highest forward isolation is needed in standby mode, a diode can be

used in series with the Ven pin to increase the switch-on threshold of the device. This can be particularly important at

elevated temperatures. Some suggested diodes in suitable packages (SOD-523F) for the evaluation board are:

-

1N914BWT-D PN fast switching diode

-

BAT43XV2-D Schottky diode

Evaluation Board & Bias Procedure

In general, sequencing of the Vd and Ven supplies is not necessary however applying Vd before or simultaneously with

Ven is recommended.

The separate through line can be used to measure the evaluation board and connector losses. These results can then

be used to de-embed the device performance from evaluation board measurements.

Figure 34: Insertion Loss – through line

Figure 35: Return Loss – through line