400DABBA0 datasheet(37/47 Pages) ONSEMI

37 / 47 page

NCP12400

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Figure 70. Block Schematic of Overpower Protection Circuit

A 5−bit A/D converter with the peak detector senses the

ac input, and its output is periodically sampled and reset, in

order to follow closely the input voltage variations. The

sample and reset events are given by the output from the ac

line unplug detector. The sensed HV pin voltage peak value

is validated when no HV edges from comparator are present

after last falling edge during 2 sample clocks. See Figure 71

for details.

Overcurrent Protection with Fault Timer

The overload protection depends only on the current

sensing signal, making it able to work with any transformer,

even with very poor coupling or high leakage inductance.

When an overcurrent occurs on the output of the power

supply, the FB loop asks for more power than the controller

can deliver, and the CS set−point reaches VILIM. When this

event occurs, an internal tfault timer is started: once the timer

times out, DRV pulses are stopped and the controller is either

latched off. This latch is released in autorecovery mode. The

controller tries to restart after tautorec. The other possibilities

of the latch release are the brown−out condition or the VCC

power on reset. The timer is reset when the CS set−point

goes back below VILIM before the timer elapses. The fault

timer is also started if the driver signal is reset by the

maximum on time. The controller also enters the same

protection mode if the voltage on the CS pin reaches 1.5

times the maximum internal set−point VCS(stop) (allows to

detect winding short−circuits) or there appears low VCC

supply. See Figure 71 for the timing diagram.

400DABBA0 数据表(PDF) 37 Page - ON Semiconductor