RAMK027

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Vishay MCB

Revision: 20-Jul-2021

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Document Number: 32583

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ELECTRICAL INTERFACE DESCRIPTION - SSI INTERFACE

Timing Diagram

OPTIONS

• Other design on request (mechanical interfaces, electrical interfaces, ...)

6 WIRES CONNECTIONS

NAME

WIRE COLOR

GND

Black

+5 V

Red

CLK+

White

CLK-

Clear

DATA+

Yellow

DATA-

Green

SSI PARAMETERS

Output code

Binary

Data differential interface

RS422 according to EIA-RS422

CLK differential interface

RS422 according to EIA-RS422

Minimum clock frequency

300 kHz

Maximum clock frequency

4 MHz

Data bit (n)

19 bits

C: consistency of all internal

magnetic cells outputs

Bit “C”: 0

 compliant /

1

 not compliant

16-0: angle

Bit “16-0”: angle value

P: parity of this bits “C” to “16”

Bit “P”: 0

 pair sum /

1

 impair sum

Master system

Sensor

+5 V

+5 V

+5 V

+5 V

100

Ω

+5 V

+5 V

GND

+5 V

DATA+

DATA-

CLK-

CLK+

t

sampling t 18.5 x tclock + tp + 500 ns

1

F

clock

t

clock =

t 500 ns

t

p = 12 μs

d 200 ns

Start of cycle

End of cycle

CLK+

CLK-

DATA+

DATA-

S

C

16

15

14

2

1

0

P

MSB

LSB