AP3108LS

Document number: DS42105 Rev. 3 - 2

13 of 16

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February 2021

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AP3108LS

Operation Description (continued)

System Protection

FOCP, SSCP, VCC OVP, OTP

The AP3108LS provides versatile protection to ensure the reliability of the power system. FOCP protection is an ultra-fast short-current protection

which is helpful to avoid catastrophic damage of the system when the secondary rectifier is short. The primary peak current will be monitored by

SENSE pin through a primary sense resistor, whenever the sampled voltage reaches the threshold of VTH-FOCP for 7 switching cycles continuously,

the FOCP protection will be active to shut down the switching pulse. SSCP might be triggered at ultra-low line voltage condition or other failure

condition that short the SENSE pin to ground. The SSCP module senses the voltage across the primary sense resistor with a delay of 4µs after

the rising edge of primary GATE signal, this sensed signal is compared with VTH-SSCP. If it is lower than VTH-SSCP for 7 switching cycles, the SSCP

protection will be triggered and the drive signal will be disabled. All these protections described above will restart the system when the VCC voltage

falls below UVLO. Although the external OTP can be easily implemented through CTRL pin, the AP3108LS still reserves the inner OTP with a

hysteresis for any necessary use.

VCC Maintain Mode

During light-load or transient-load condition, VFB will drop and be lower than 1.2V, thus the PWM drive signal will be stopped, and there is no more

new energy transferring to the output. Therefore, the IC supply voltage may reduce to the UVLO threshold voltage and system may enter the

unexpected restart mode. To avoid this, the AP3108LS holds a so-called VCC maintain mode which can supply energy to VCC.

When VCC decreases to a setting threshold as VM, the VCC maintain mode will be awaked and a charging current of ICHARGE-H will flow to the VCC

pin. With VCC maintain mode, the VCC is not easy to touch the shutdown threshold during the startup process and transient load condition. This will

also simplify the system design. The minimum VCC voltage is suggested to be designed a little higher than VCC maintain threshold thus can

achieve the best balance between the power loss and step load performance.

Leading-Edge Blanking Time

A narrow spike on the leading edge of the current waveform can usually be observed when the power MOSFET is turned on. A 250ns leading-

edge blank is built-in to prevent the false-trigger caused by the turn-on spike. During this period, the current limit comparator and the PWM

comparator are disabled and the gate driver cannot be switched off.

At the time of turning-off the MOSFET, a negative undershoot (maybe larger than -0.3V) can occur on the SENSE pin. So it is strongly

recommended to add a small RC filter or at least connect a resistor “R” on this pin to protect the IC (Shown as Figure 9).

SENSE

GATE

Large undershoot (more than

-0.3V) may damage the SENSE pin

R

C

Necessary

Figure 9