ICS93701 datasheet(1/9 Pages) ICST

部件名	ICS93701

功能描述	DDR Phase Lock Loop Clock Driver

PDF	9 Pages

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制造商	ICST [Integrated Circuit Systems]

网页	http://www.icst.com

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1 / 9 page

Integrated

Circuit

Systems, Inc.

ICS93701

0417B—10/29/02

Block Diagram

DDR Phase Lock Loop Clock Driver

Pin Configuration

48-Pin TSSOP

Recommended Application:

DDR Clock Driver

Product Description/Features:

•

Low skew, low jitter PLL clock driver

•I

2C for functional and output control

•

Feedback pins for input to output synchronization

•

Spread Spectrum tolerant inputs

Switching Characteristics:

•

PEAK - PEAK jitter (66MHz): <120ps

•

PEAK - PEAK jitter (>100MHz): <75ps

•

CYCLE - CYCLE jitter (66MHz):<120ps

•

CYCLE - CYCLE jitter (>100MHz):<65ps

•

OUTPUT - OUTPUT skew: <100ps

•

DUTY CYCLE: 49.5% - 50.5%

•

Slew rate: 1V/ns - 2V/ns

GND

CLKC0

CLKT0

VDD

CLKT1

CLKC1

GND

CLKC2

CLKT2

VDD

SCLK

CLK_INT

CLK_INC

AVDD

AGND

GND

CLKC3

CLKT3

VDD

CLKT4

CLKC4

GND

VDDI C

2

GND

CLKC5

CLKT5

VDD

CLKT6

CLKC6

GND

CLKC7

CLKT7

VDD

SDATA

FB_INC

VDD

FB_OUTT

GND

CLKC8

CLKT8

VDD

CLKT9

CLKC9

GND

FB_INT

FB_OUTC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

Functionality

S

T

U

P

N

IS

T

U

P

T

U

O

e

t

a

t

S

L

P

D

V

AT

N

I

_

K

L

CC

N

I

_

K

L

CT

K

L

CC

K

L

CT

T

U

O

_

B

FC

T

U

O

_

B

F

V

5

.

2

)

m

o

n

(

LH

L

H

L

H

n

o

V

5

.

2

)

m

o

n

(

HL

H

L

H

L

n

o

V

5

.

2

)

m

o

n

(

)

z

H

M

0

2

<

)

1

(

ZZ

Z

f

o

PLL