STM32H757II datasheet(21/251 Pages) STMICROELECTRONICS

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DS12931 Rev 1

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STM32H757xI

Functional overview

3.1.2

Arm® Cortex®-M4 with FPU

The Arm® Cortex®-M4 processor is a high-performance embedded processor which

supports DSP instructions. It was developed to provide an optimized power consumption

MCU, while delivering outstanding computational performance and low interrupt latency.

The Arm® Cortex®-M4 processor is a highly efficient MCU featuring:

•

3-stage pipeline with branch prediction

•

Harvard architecture

•

32-bit System (S-BUS) interface

•

32-bit I-BUS interface

•

32-bit D-BUS interface

The Arm® Cortex®-M4 processor also features a dedicated hardware adaptive real-time

accelerator (ART Accelerator™). This is an instruction cache memory composed of sixty-

four 256-bit lines, a 256-bit cache buffer connected to the 64-bit AXI interface and a 32-bit

interface for non-cacheable accesses.

3.2

Memory protection unit (MPU)

The devices feature two memory protection units. Each MPU manages the CPU access

rights and the attributes of the system resources. It has to be programmed and enabled

before use. Its main purposes are to prevent an untrusted user program to accidentally

corrupt data used by the OS and/or by a privileged task, but also to protect data processes

or read-protect memory regions.

The MPU defines access rules for privileged accesses and user program accesses. It

allows defining up to 16 protected regions that can in turn be divided into up to 8

independent subregions, where region address, size, and attributes can be configured. The

protection area ranges from 32 bytes to 4 Gbytes of addressable memory.

When an unauthorized access is performed, a memory management exception is

generated.

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