APR340

Document number: DS43230 Rev. 3 - 2

7 of 9

www.diodes.com

May 2021

© Diodes Incorporated

APR340

Synchronous Rectification Principle Description (continued)

VDD

The VDD is the output voltage of the Pulse Linear Regulator (PLR) or the Low Dropout Regulator (LDO). It provides bias voltage for the controller.

A capacitor (typically 4.7

μF) should be connected between the VDD pin and GND pin.

A Pulse Linear Regulator is integrated in the controller to provide voltage to the VDD pin of the APR340. With the PLR, the APR340 can operate at

a low voltage output condition, in which the system output voltage may drop to as low as 2V. The bias voltage will change from the PLR to the

LDO when the system output voltage is higher than 4.75V. In this case, the system output provides voltage to the APR340

’s VDD through the

internal LDO.

Ordering Information

Package

Product Name

W6 : SOT26

7 : 7" Tape & Reel

APR340 X

– X

Packing

Package

Temperature Range

Part Number

Marking ID

7

”Tape and Reel

Quantity

Part Number Suffix

SOT26

-40°C to +85°C

APR340W6-7

CY

3000/Tape and Reel

-7

Marking Information

1

2

3

6

4

XX Y W X

XX : Identification Code

Y : Year 0 to 9

X : Internal Code

(Top View)

5

W : Week : A to Z : 1 to 26 Week;

a to z : 27 to 52 Week; z Represents

52 and 53 Week