All specifications are subject to change without notice.

FNETHE025

Rev F

07/13/12

3.3V CMOS Low-Jitter 25 MHz GbE XO

FNETHE025

FNETHE025

025

TM

Output Enable / Disable Function

Min.

Input Voltage (pin 1), Output Enable

0.7 VDD

Vor open

Input Voltage (pin 1), Output Disable (low power standby)

0.3 VDD

VOutput is Hi-Z

Internal Pullup Resistance

30

Output Disable Delay

50

ns

Output Enable Delay

2ms

Electrical Performance

Min.

Output Frequency

25

MHz

Supply Voltage VDD

2.97

3.3

3.63

V

Supply Current, Output Enabled

15

mA

Supply Current, Output Disabled

10

μA

Frequency Stability

±25

ppm

See Note 1 below

Operating Temperature Range

-20

+70

°C

Output Logic 0, VOL

10% VDD

V

Output Logic 1, VOH

90% VDD

V

Output Load

15

pF

Duty Cycle

45

55

%

Measured 50% VDD

Rise and Fall Time

7

ns

Measured 20/80% of waveform

Jitter, Phase, RMS(1-

1

ps

12kHz~20MHz Frequency Band

Jitter, pk-pk

50

ps

100.000 random periods

Notes:

1.

Stability includes all combinations of operating temperature, load changes, rated input (supply) voltage changes, initial calibration tolerance (25°C),

aging (1 year at 25°C average effective ambient temperature), shock and vibration.

Absolute Maximum Ratings

Min.

Storage Temperature

-55

+125

°C

2

12-0051