A Product Line of

Diodes Incorporated

PI2DPX2023

7

www.diodes.com

July 2022

Diodes Incorporated

PI2DPX2023

Document Number DS43532 Rev 4-2

I/O Termination Resistance under Different Conditions

Symbol

Parameter

Resistance

Units

RX Terminal

Rin-pd

Input res at EN=0

78k to VbiasRx

Ω

Rin-Active

Input res at active mode condition

50 to VbiasRx1

Ω

Rin-DP-standby

Input res in DP standby mode

78k to VbiasRx

Ω

Rin-DP-active

Input res in DP active mode

50 to VbiasRx1

Ω

Rin-DP-D3

Input res in DP D3 mode

78k to VbiasRx

Ω

TX Terminal

Rout-pd

Output res at EN=0

78k to VbiasTx

Ω

Rout-Active

Output res at active mode condition

50 to VDD

Ω

Rout-DP-standby

Output res in DP standby mode

78k to VbiasTx

Ω

Rout-DP-active

Output res in DP active mode

50 to VDD

Ω

Rout-DP-D3

Output res in DP D3 mode

78k to VbiasTx

Ω

Notes:

1) The value of Rin will be updated only after the receiver evaluation. Thus, the value can be 50Ω or 78kΩ.

2) The value of Rout will be updated only after the receiver evaluation. Thus, the value can be 50Ω or 6kΩ.

DisplayPort Mode

By default, all channels will go to active mode if HPD bit = 1. The ON/OFF of each DP channel is controlled by the Aux lane count.

Operation Mode

ML_TX_x_n

ML_TX_x_p

Source

Connector

Sink

Connector

Sink

Connector

Tx

Rx

50

50

Vbias_Tx

50

50

Vbias_Rx

Upstream device

Downstream device

ML_TX_x_n

ML_TX_x_p

ML_RX_x_n

ML_RX_x_p

ML_RX_x_n

ML_RX_x_p

Source

Connector

Tx

Rx

50

50

Vbias_Tx

50

50

Vbias_Rx

100k-1M

100k-1M

Figure 2. DisplayPort Main Link Connection Diagram