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WM8785GEDS/V 数据表(PDF) 9 Page - Wolfson Microelectronics plc

部件名 WM8785GEDS/V
功能描述  24-Bit, 192kHz Stereo ADC
PDF  31 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8785GEDS/V 数据表(HTML) 9 Page - Wolfson Microelectronics plc

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Pre-Production
WM8785
w
PP Rev 3.0 December 2005
9
AUDIO INTERFACE TIMING – SLAVE MODE, PCM DATA
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25
oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
25
ns
LRCLK set-up time to BCLK rising edge
tLRSU
10
ns
LRCLK hold time from BCLK rising edge
tLRH
10
ns
DOUT propagation delay from BCLK falling edge
tDD
0
11
ns
CONTROL INTERFACE TIMING – 3-WIRE MODE
CSB
SCLK
SDIN
t
CSL
t
DHO
t
DSU
t
CSH
t
SCY
t
SCH
t
SCL
t
SCS
LSB
t
CSS
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DVDD = 3.3V, DVDD = 3.3V, DGND = 0V, TA = +25
oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise
stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
tSCS
80
ns
SCLK pulse cycle time
tSCY
200
ns
SCLK pulse width low
tSCL
80
ns
SCLK pulse width high
tSCH
80
ns
SDIN to SCLK set-up time
tDSU
40
ns
SCLK to SDIN hold time
tDHO
40
ns
CSB pulse width low
tCSL
40
ns
CSB pulse width high
tCSH
40
ns
CSB rising to SCLK rising
tCSS
40
ns
Pulse width of spikes that will be suppressed
tps
4
6
ns



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