AP64100

Document number: DS43571 Rev. 1 - 2

3 of 26

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March 2021

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AP64100

Pin Descriptions

Pin Name

Pin Number

Function

BST

1

High-Side Gate Drive Boost Input. BST supplies the drive for the high-side N-Channel power MOSFET. A 100nF

capacitor is recommended from BST to SW to power the high-side driver.

VIN

2

Power Input. VIN supplies the power to the IC as well as the step-down converter power MOSFETs. Drive VIN with a

3.8V to 40V power source. Bypass VIN to GND with a suitably large capacitor to eliminate noise due to the switching

of the IC. See Input Capacitor section for more details.

EN

3

Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator and low to

turn it off. Connect to VIN or leave floating for automatic startup. The EN has a precision threshold of 1.18V for

adjusting the UVLO. See Enable section for more details.

RT/CLK

4

Resistor Timing and External Clock. This pin can be used to control the switching frequency by setting the internal

oscillator frequency or by synchronizing to an external clock. Connect a resistor from RT/CLK to GND to set the

internal oscillator frequency. An external clock can be input directly to the RT/CLK pin and the internal oscillator

synchronizes to the external clock frequency using a PLL. If the external clock edges stop, the operating mode

automatically returns to the resistor frequency setting.

See Adjusting Switching Frequency section for more details.

FB

5

Feedback sensing terminal for the output voltage. Connect this pin to the resistive divider of the output.

See Setting the Output Voltage section for more details.

COMP

6

Compensation. Connect an external RC network to the COMP pin to adjust the loop response.

See External Loop Compensation Design section for more details.

GND

7

Power Ground.

SW

8

Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC filter

from SW to the output load.

EXPOSED

PAD

9

Heat dissipation path of the die. The exposed thermal pad must be electrically connected to GND and must be

connected to the ground plane of the PCB for proper operation and optimized thermal performance.