FT900L-R datasheet(30/67 Pages) BRIDGETEK

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FT900

/1/2/3 Revision C Embedded Microcontroller Datasheet

Version 1.0

Document No. BRT_000172 Clearance No.: BRT#087

The watchdog timer is controlled from the main clock. The watchdog can be initialized with a 5-bit

firmware. As the timer decrements, an interrupt occurs when the timer rolls over. Once started and

initialized the watchdog can’t be stopped. It can only be cleared by writing into a register.

The four user timers can be controlled from the main clock, each timer has its own 16-bit pre-scaler.

These timers can be started, stopped and cleared / initialized. The pre-scalers can be cleared or initialised

the same way.

The current value of all timers/pre-scalers can be read from a common register one-at-a-time

(multiplexed access).

All timers can count up/down and signal an interrupt when the timer rolls over. The timers can also be

configured to be one-shot or in continuous mode. They are initialised from a common register one-at-a-

time (multiplexed access).

If the user timer has already started using its pre-scaler, it cannot be cleared and the command is

ignored. Each of the pre-scalers automatically stops after it is cleared individually. It also starts

automatically when the corresponding user timer starts using it.

4.16.1

Features



Four user timers with individual pre-scaler.



Supports 16-bit pre-scaler with system clock reference.



Supports individual timer interrupt generated.



Supports one-shot and continuous count for timer.



Supports 32-bit counter watchdog.



Supports watchdog interrupt generated.

4.17

I2S Interface

The FT900 I2S interface supports both Master and Slave modes. The formats supported are I2S, Left

Justified and Right Justified.

In Master mode, two clock sources are to be provided externally. One is 24.576MHz and the other is

22.5792MHz. The LRCLK, BCLK and MCLK as output signals will be generated by the Master based on

sampling rate and data bit length.

In Slave mode, the LRCLK and BCLK are input signals to the FT900. The MCLK source is not used in this

case. The application can configure the two clock source pins (I2SM_CLK22, I2SM_CLK24) to GPIO

operation.

4.17.1

Features



Configure I2S interface as master or slave.



Support I2S, Left Justified and Right Justified format.



Support different sample rates: 11.025 kHz, 22.050 kHz, 44.1 kHz, 16 kHz, 32 kHz, 48 kHz, 96

kHz, 192 kHz and 384 kHz.



Support different audio data bit length: 16 bits, 20 bits, 24 bits and 32 bits.



2kB FIFO for I2S receiver and 2kB FIFO for transfer audio data.



Support FIFO flow control.



Support master clock sources: 24.576MHz and 22.5792MHz.

4.18

Camera Parallel Interface (Data Capture)

The Camera Parallel Interface (CPI) implements an 8-bit parallel link from an image sensor to the FT900.

The interface will provide a clock to the external camera module at a Max rate of 25MHz.

Camera control signals are VSYNC, HREF and PCLK. The VSYNC signal determines when a new frame

begins. The HREF signal represents the period of data transfer of a row in the transmitted frame. When

the HREF signal is active, there is valid data over the data lines every pixel clock (PCLK) cycle. The PCLK

signal indicates a valid data byte over the data lines and it is used as a transfer trigger.

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