PFS7523L datasheet(3/36 Pages) POWERINT

3 / 36 page

Rev. A 06/15

PFS7523-7529/7533-7539

www.power.com

Pin Functional Description

BIAS POWER (VCC) Pin:

This is a 10.2-15 VDC [operating, 12 V typical] bias supply used to

power the IC. The bias voltage must be externally clamped to

prevent the BIAS POWER pin from exceeding 15 VDC to ensure

long-term reliability.

REFERENCE (REF) Pin:

This pin is connected to an external bypass capacitor and is used to

program the IC for either FULL or EFFICIENCY power mode. The

external capacitor is connected between the REFERENCE and SIGNAL

GROUND [G] pins. Note: the return trace to G must not be shared with

other return traces with a potential for large return currents during

surge events. The REFERENCE pin has two valid capacitor values to

select ‘Full’ (1.0 µF ±20%) and ‘Efficiency’ (0.1 µF ±20%) power

modes.

SIGNAL GROUND (G) Pin:

Discrete components used in the feedback circuit, including loop

compensation, decoupling capacitors for the BIAS POWER (VCC),

REFERENCE (REF) and VOLTAGE MONITOR (V) must be referenced to

the SIGNAL GROUND (G) pin. The SIGNAL GROUND pin is also

connected to the tab of the device. The SIGNAL GROUND pin should

not be tied directly to the SOURCE pin external to the IC.

VOLTAGE MONITOR (V) Pin:

The VOLTAGE MONITOR pin is tied to the rectified high-voltage DC

rail through a 100:1, 1% high-impedance resistor divider to minimize

power dissipation and standby power consumption. The recommend-

ed resistance value is between 8 MΩ and 16 MΩ. Modifying this

divider ratio affects peak power limit, brown-in/out thresholds and

will degrade input current quality (reduce power factor and increase

THD). A small ceramic capacitor forming an 80 µs nominal time-

constant is required from the VOLTAGE MONITOR pin to the SIGNAL

GROUND pin to bypass any switching noise present on the rectified

DC bus.

This pin also features brown-in/out detection thresholds and

incorporates a weak current source into the IC in order to act as a

pull-down in the event of an open circuit condition.

COMPENSATION (C) Pin:

This pin is used for loop pole/zero compensation of the OTA error

amplifier via the connection of a network of capacitors and a resistor

between the COMPENSATION pin and SIGNAL GROUND pin. The

COMPENSATION pin connects internally to the output of the OTA error

amplifier and the input to the on-time and off-time controllers.

FEEDBACK (FB) Pin:

This pin is connected to the main voltage regulation feedback resistor

divider network and is also used for fast over and undervoltage

protection. This pin also detects the presence of the feedback

voltage divider network at start-up and during operation. The divider

ratio should be the same as the VOLTAGE MONITOR pin for proper and

optimized power limit and power factor. A large upper resistor

between 8 MΩ and 16 MΩ ±1% is recommended. A small ceramic

capacitor between FEEDBACK and SIGNAL GROUND, forming a nominal

80 µs time-constant with the bottom resistor, is required.

POWER GOOD (PG) Pin:

Use of the PG function is optional. The POWER GOOD pin is an

active low, open-drain connection which sinks current when the

output voltage is in regulation. At start-up, once the FEEDBACK pin

voltage has risen to ~95% of the internal reference voltage, the

POWER GOOD pin is asserted low.

After start-up, the output voltage threshold at which the PG signal

becomes high-impedance depends on the threshold programmed by

the POWER GOOD THRESHOLD pin resistor. When not in use, the

POWER GOOD pin is left unconnected.

POWER GOOD THRESHOLD (PGT) Pin:

This pin is used to program the output voltage threshold at which the

PG signal becomes high-impedance representing the PFC stage falling

out of regulation. The low threshold for the PG signal is programmed

with a resistor between the POWER GOOD THRESHOLD and SIGNAL

GROUND pins. Tying POWER GOOD THRESHOLD to the REFERENCE

pin disables the power good function (i.e. POWER GOOD pin remains

high impedance).

SOURCE (S) Pins:

These pins are the source connection of the power switch as well as

the negative bulk capacitor terminal connection.

PI-7225-061615

H Package (eSIP-16D)

(Front View)

H Package

(eSIP-16D)

(Back View)

L Package (eSIP-16G)

(Front View)

Exposed Pad (Backside)

Internally Connected to

GROUND (G) Pin

Exposed Metal (Both H and L

Packages) (On Package Edge)

Internally Connected to G Pin

Pin 1 I.D.

Exposed Pad

(Backside)

Not Shown

Figure 3. Pin Configuration.

PFS7523L 数据表(PDF) 3 Page - Power Integrations, Inc.

PFS7523L 数据表(HTML) 3 Page - Power Integrations, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表下载