PFS7524L datasheet(8/36 Pages) POWERINT

8 / 36 page

Rev. A 06/15

PFS7523-7529/7533-7539

www.power.com

The power good comparator has an internal 81 µs de-glitch filter

PGD) to prevent noise events from falsely triggering the programmed

PG- threshold.

In the event a load fault prevents the boost from achieving regulation

(above ~95% of the set output voltage threshold) the PG function will

remain in the high-impedance state and will not indicate when an

output voltage has fallen below the user programmed V

PG- threshold.

The V

PG- user programmed threshold is enabled once the VPG+

threshold has been reached.

If the POWER GOOD THRESHOLD programming pin is tied to

REFERENCE pin, the power good function is disabled and PG remains

in the high-impedance (‘off’) state. This is the preferred configuration

when PG is not in use. If the POWER GOOD THRESHOLD pin is shorted

to the SIGNAL GROUND pin, the PG signal will transition to the ‘on’

state at V

PG+ and remain low (‘on’) until the PFC output voltage has

fallen below the V

FB_UV threshold for greater than tFB_UV seconds.

Similar to the disable condition described above, if the value of the

PGT resistor is such that the V

PG- threshold is greater than the VPG+

threshold, the PG signal will latch off and remain in the high-imped-

ance off-state.

The Power Good function is not valid under the following conditions:

A. VCC or VREF are not in a valid range of operation. VCC below

UVLO- or VREF below REF

UV- the power good function is not valid

with the POWER GOOD pin in a high-impedance state.

B. Power Good will go to high-impedance state when a soft- shut-

down is initiated by an over-temperature fault to provide early

indication to secondary circuits of an OT fault.

C. PGT is outside the valid programming range of between 225 V and

360 V. PGT voltages above this range, including PGT floating, will

prevent PG from transitioning to active pull-down. PGT voltages

below this range result in PG deassertion at the output undervolt-

age (V

FB_UV) threshold.

D. Once the start-up sequence check has passed and the converter

goes into start-up, if PGT is opened, then the PG signal will

remain latched in the high-impedance state until the controller is

reset.

Figure 11. Power Good Function Description.

Selectable Power Limit

The capacitor on the REFERENCE pin allows user selection between

’full’ and ‘efficiency’ power limit for each device. The ‘efficiency’

power mode will permit user selection of a larger device for a given

output power requirement for increased conversion efficiency.

In ‘full’ power mode the REFERENCE pin capacitor is 1.0 µF ±20%

and the ‘efficiency’ power limit mode is selected with a 0.1 µF ±20%

capacitor.

If the REFERENCE pin is accidentally shorted to ground, the IC will

disable switching and remain disabled until all conditions for the

start-up sequence are satisfied.

If the REFERENCE pin is open-circuit, the absence of a bypass

capacitor will prevent start-up. During operation, an open-circuit may

result in enough REFERENCE pin noise to result in a VREF REF

UV- shut-

down.

Protection Modes

Brown-In Protection (V

BR+)

The VOLTAGE MONITOR pin features an input line under-voltage

detection to limit the minimum start-up voltage. This detection

threshold will inhibit the device from starting at input AC voltages

below brown-in and above input peak voltages of 400 V

PK.

Brown-Out Protection (V

BR-)

The VOLTAGE MONITOR pin features a brown-out protection mode

wherein the HiperPFS-3 will turn-off when the VOLTAGE MONITOR

pin voltage is below the line undervoltage threshold (V

BR-) for a period

exceeding t

BRWN_OUT (brown-out debounce period). In the event a

single half-line cycle is missing (normal operating line frequency is

47 Hz to 63 Hz) the brown-out detection will not be initiated. Once

brown-out has been triggered, the HiperPFS-3 soft-shutdown

gradually reduces the internal error-voltage to zero volts over a period

of 1 ms to ramp the power MOSFET on-time to zero. The onset of

this soft-shutdown is aligned to the next line cycle zero crossing to

minimize reactive component di/dt transients and allow time for the

energy stored within the boost choke as well as the input EMI filter to

dissipate. This helps minimize voltage transients after the bridge

rectifier, which helps to prevent false restarts. The device will

Output Voltage

Rising

Output Voltage

Falling

tPGD

tPG

PG = High Impedance

PG = On-State

Set internally

by VPG+

95% VOUT (365 V)

100% VOUT (385 V)

87.5% VOUT (337 V)

Set externally

by RPGT

0875

385

337

PI-7229-061615

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