PFS7623L datasheet(4/38 Pages) POWERINT

4 / 38 page

Rev. F 08/20

PFS7x23-7x29/7633-7636

www.power.com

the SIGNAL GROUND (G) pin. The SIGNAL GROUND pin is also

connected to the tab of the device. The SIGNAL GROUND pin should

not be tied directly to the SOURCE pin external to the IC.

VOLTAGE MONITOR (V) Pin

The VOLTAGE MONITOR pin is tied to the rectified high-voltage DC

rail through a 100:1, 1% high-impedance resistor divider to minimize

power dissipation and standby power consumption. The recommended

resistance value is between 8 MW and 16 MW. Changing this divider

ratio affects peak power limit, brown-in/out thresholds and will

degrade input current quality (reduce power factor and increase

THD). A small ceramic capacitor forming an 80 ms nominal time-

constant must be connected between the VOLTAGE MONITOR pin to

the SIGNAL GROUND pin to bypass any switching noise present on

the rectified DC bus.

This pin also features brown-in/out detection thresholds and

incorporates a weak current source that acts as a pull-down in the

event of an open circuit condition.

COMPENSATION (C) Pin

This pin is used for loop pole/zero compensation of the OTA error

amplifier via the connection of a network of capacitors and a resistor

between the COMPENSATION pin and SIGNAL GROUND pin. The

COMPENSATION pin connects internally to the output of the OTA

error amplifier and the input to the on-time and off-time controllers.

FEEDBACK (FB) Pin

This pin is connected to the main voltage regulation feedback resistor

divider network and is also used for fast over and undervoltage

protection. This pin also detects the presence of the feedback

voltage divider network at start-up and during operation. The divider

ratio should be the same as the VOLTAGE MONITOR pin for proper

and optimized power limit and power factor. A large upper resistor

between 8 MW and 16 MW ±1% is recommended. A small ceramic

capacitor between FEEDBACK and SIGNAL GROUND, forming a

nominal 80 ms time-constant with the bottom resistor, is required.

POWER GOOD (PG) Pin

Use of the PG function is optional. The POWER GOOD pin is an

active low, open-drain connection which sinks current when the

output voltage is in regulation. At start-up, once the FEEDBACK pin

voltage has risen to ~95% of the internal reference voltage, the

POWER GOOD pin is asserted low.

After start-up, the output voltage threshold at which the PG signal

becomes high-impedance depends on the threshold programmed by

the POWER GOOD THRESHOLD pin resistor. When not used, the

POWER GOOD pin is left unconnected.

POWER GOOD THRESHOLD (PGT) Pin

This pin is used to program the output voltage threshold at which the

PG signal becomes high-impedance representing the PFC stage falling

out of regulation. The low threshold for the PG signal is programmed

with a resistor between the POWER GOOD THRESHOLD and SIGNAL

GROUND pins. Tying the POWER GOOD THRESHOLD to the

REFERENCE pin disables the power good function (i.e. POWER GOOD

pin remains high impedance).

SOURCE (S) Pins

These pins are the source connection of the power switch as well as

the negative bulk capacitor terminal connection.

DRAIN (D) Pin

This is the drain connection of the internal power switch.

Boost Diode Cathode (K) Pin

This is the cathode connection of the internal Qspeed diode.

Figure 3. Pin Configuration.

Pin 1 I.D.

PI-8616-081320

Note pin 16 is NC for PFS76xx and K pin for PFS772x.

H Package (eSIP-16D)

(Front View)

C Package (InSOP-24B)

(Top View)

C Package (InSOP-24B)

(Bottom View)

H Package (eSIP-16D)

(Back View)

L Package (eSIP-16G)

(Front View)

Exposed Pad (Backside of

Both H and L Packages)

Internally Connected to

GROUND (G) Pin

Exposed Pad

(Backside)

Not Shown

Exposed Pad

Connected to

DRAIN (D) Pin

NC 13

NC 14

NC 15

D 16-19

S 24

12 G

11 NC

10 NC

9 NC

8 PGT

7 PG

6 FB

5 C

4 V

3 REF

2 G

1 VCC

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