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PRELIMINARY

XRT83SL216

REV. P1.0.3

16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

19

2.0 TRANSMIT PATH LINE INTERFACE

The transmit path consists of 16 independent E1 transmitters. The following section describes the complete

transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A simplified block diagram of the

transmit path is shown in Figure 10.

2.1

TCLK/TPOS/TNEG Digital Inputs

In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG can

be tied to ground. The XRT83SL216 can be programmed to sample the inputs on either edge of TCLK. By

default, data is sampled on the falling edge of TCLK. To sample data on the rising edge of TCLK, set TCLKinv

to "1" in the appropriate global register. Figure 11 is a timing diagram of the transmit input data sampled on the

falling edge of TCLK. Figure 12 is a timing diagram of the transmit input data sampled on the rising edge of

TCLK. The timing specifications are shown in Table 2.

HDB3

Encoder

Tx Jitter

Attenuator

Timing

Control

Tx Pulse Shaper

Line Driver

TTIP

TRING

TCLK

TNEG

TPOS

TCLK

TPOS

or

TNEG

TCLK

R

TCLK

F

T

HO

T

SU

TCLK

TPOS

or

TNEG

TCLK

F

TCLK

R

T

HO

T

SU