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L6590A

Figure 27. PWM Control internal schematic

Oscillator and PWM Control

PWM regulation is accomplished by implementing voltage mode control. As shown in fig. 27, this block includes

an oscillator, a PWM comparator, a PWM latch and a PWM control input.

The oscillator operates at a frequency internally fixed at 65 kHz with a precision of ± 10%. This value has been

selected so that the second harmonic falls below 150 kHz, beyond which some international standards envisage

more severe limits. The maximum duty cycle is limited at 70% typ.

The PWM latch (reset dominant) is set by the clock pulses of the oscillator and is reset by either the PWM com-

parator or the Overcurrent comparator. The inverting input of the PWM comparator is externally available (pin

4, COMP) in order for an optocoupler-based circuit to close the control loop that regulates the converter's output

voltage.

In case of overcurrent the voltage at pin COMP saturates high and the conduction of the power MOSFET is

stopped by the OCP comparator instead of the PWM comparator.

Under zero load conditions the COMP pin is close to its low saturation and the gate drive delivers as short pulses

as it can, limited by internal delays. They are however too long to maintain the long-term energy balance, thus

from time to time some cycles need being skipped and the operation becomes asynchronous. This is automat-

ically done by the control loop.

Standby Function

The standby function, optimized for flyback topology, automatically detects a light load condition for the convert-

er and decreases the oscillator frequency. The normal oscillation frequency is automatically resumed when the

output load builds up and exceeds a defined threshold.

This function allows to minimize power losses related to switching frequency, which represent the majority of losses

in a lightly loaded flyback, without giving up the advantages of a higher switching frequency at heavy load.

The Standby function is realized by monitoring the peak current in the power switch. If the load is low that it does

not reach a threshold (80 mA typ.), the oscillator frequency will be set at 22 kHz typ.

When the load demands more power and the peak primary current exceeds a second threshold (190 mA typ.)

the oscillator frequency is reset at 65 kHz. This 110 mA hysteresis prevents undesired frequency change when

power is such that the peak current is close to either threshold.

The signal coming from the sense circuit is digitally filtered to avoid false triggering of this function as a result of

large load changes or noise.

L6590A

Clock

+

-

from OCP

comparator

COMP

S

R

Q

Max. Duty cycle

OSCILLATOR

to gate

driver

PWM

1mA