IN100-Q1-R-RC1F datasheet(39/49 Pages) ETC

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N1EDOC-DS-IN100-EN-V1.3

7. Layout

To ensure device performance, it is recommended to follow the general printed circuit board

layout guidelines described below.

7.1.Layer stack-up

The recommendations in this document refer to the 2-layer standard flame retardant 4 (FR4)

materials, a technology commonly used in commercial applications.

Table 20 : PCB layer stack-up

Layer

Purpose

Material

Thickness Thickness

control

Adjust to get

desired total

PCB thickness

Top layer

+Plating

Signal

1/2 oz Cu

1.4

Yes

Dielectric

FR4

28.7

Yes

Bottom Layer +

Plating

Signal/power

1/2 oz Cu

1.4

Yes

Total thickness

(mil)

7.2. Crystal

7.2.1. 26MHz crystal

When there is a high-speed 26MHz crystal in the system, the parasitics associated with the clock

trace affect the frequency of oscillation, so the crystal should be placed as close as possible to

the device. Traces that are too wide can cause excessive capacitance, while traces that are too

narrow can cause excessive parasitic inductance of the clock traces. For short clock traces, use

a trace width of approximately 10 mils (0.010 inches or 0.254 mm). Keep the crystal tuning

capacitor close to the crystal pad.

Avoid passing through the crystal lines on adjacent layers. Keep the ground plane below the

crystal line to improve the return path. Try to keep the parasitic capacitances on both crystal lines

equal. This can be done by keeping their lengths and widths equal.

7.2.2. 32.768kHz crystal

The slow clock signal line must be as short as possible. The trace of the slow clock signal should

have a ground plane on each side of the signal trace to reduce unwanted signal coupling. In order

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