XM014035B datasheet(21/101 Pages) XMOS

21 / 101 page

XU6--FB6 Datasheet

When the device comes out of reset, the processor will attempt to boot within a very short

period of time. If booting from external ash, ensure that there is enough time between

before RST_N coming up for the external ash to settle.

An independent watchdog runs from the input clock pin XIN. It can be set to take the

chip into reset when the watchdog has not been updated or cleared in time. The

bit watchdog timer with a 6-bit divider provides accuracies of between input clock and

66 input clocks, and a time-out of between input clock and 68,,6 input clocks

(just over

seconds with a

MHz input crystal). The watchdog is set-up through the

watchdog registers (Appendix D. -D. )

Boot Procedure

The xCORE Tile Tile boot procedure is illustrated in Figure . If the secure-boot bit of the

security register (which resides at pre-dened locations in OTP, see Section . ) is set,

the device boots from OTP. Otherwise it boots from external device(s) according to boot

source pin values XD, XD, and XD6 (see Figure ). The boot pins are sampled

shortly after reset with the internal weak pull-downs enabled on those pins. In typical

use, a boot mode other than QSPI Flash can be selected by using one or more pull-ups

on those pins. Care should be taken if other external devices are connected to this port

that the boot mode is selected correctly.

Primary Boot

Copy OTP contents

to RAM

Load RAM according

to boot source pins

secure boot

bit set?

yes

Start

Execute code from

base of RAM

Figure

Boot

procedure

The boot image provided by an external device has the following format:

-bit program size s in words.

Program consisting of s × 4 bytes.

-bit CRC, or the value xDABE to indicate that no CRC check should be per-

formed.

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