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DRA821U2...ALM 数据表(PDF) 102 Page - Texas Instruments |
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DRA821U2...ALM 数据表(HTML) 102 Page - Texas Instruments |
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102 / 252 page  7.6.6 ADC12BT Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BALL NAMES in Mode 0: MCU_ADC0_AIN[7:0] BALL NUMBERS: J18 / H17 / K18 / J17 / M17 / K17 / L18 / L17 VMCU_ADC0_AIN[7:0] Full-scale Input Range VSS VDDA (2) V DNL Differential Non-Linearity -1 0.5 4 LSB INL Integral Non-Linearity ±1 ±4 LSB LSBGAIN-ERROR Gain Error ±2 LSB LSBOFFSET-ERROR Offset Error ±2 LSB CIN Input Sampling Capacitance 5.5 pF SNR Signal-to-Noise Ratio Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 70 dB THD Total Harmonic Distortion Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 75 dB SFDR Spurious Free Dynamic Range Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 80 dB SNR(PLUS) Signal-to-Noise Plus Distortion Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 69 dB RMCU_ADC0_AIN[0:7] Input Impedance of MCU_ADC0_AIN[7:0] f = input frequency [1/((65.97 × 10–-12) × fSMPL_CLK)] Ω IIN Input Leakage MCU_ADC0_AIN[7:0] = VSS 5 μA MCU_ADC0_AIN[7:0] = VDDA_ADC_MCU 10 μA Sampling Dynamics FSMPL_CLK SMPL_CLK Frequency 60 MHz tC Conversion Time 13 ADC0 SMPL_CLK Cycles tACQ Acquisition time 2 257 ADC0 SMPL_CLK Cycles TR Sampling Rate ADC0 SMPL_CLK = 60 MHz 4 MSPS CCISO Channel to Channel Isolation 100 dB General Purpose Input Mode (1) VIL Input Low Voltage 0.35 × VDDA (2) V VILSS Input Low Voltage Steady State 0.35 × VDDA (2) V VIH Input High Voltage 0.65 × VDDA (2) V VIHSS Input High Voltage Steady State 0.65 × VDDA (2) V DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 102 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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