数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

74ALVT162821 数据表(PDF) 4 Page - NXP Semiconductors

部件名 74ALVT162821
功能描述  2.5V/3.3V 20-bit bus-interface D-type flip-flop; positive-edge trigger with 30ohm termination resistors 3-State
PDF  12 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

74ALVT162821 数据表(HTML) 4 Page - NXP Semiconductors

  74ALVT162821 Datasheet HTML 1Page - NXP Semiconductors 74ALVT162821 Datasheet HTML 2Page - NXP Semiconductors 74ALVT162821 Datasheet HTML 3Page - NXP Semiconductors 74ALVT162821 Datasheet HTML 4Page - NXP Semiconductors 74ALVT162821 Datasheet HTML 5Page - NXP Semiconductors 74ALVT162821 Datasheet HTML 6Page - NXP Semiconductors 74ALVT162821 Datasheet HTML 7Page - NXP Semiconductors 74ALVT162821 Datasheet HTML 8Page - NXP Semiconductors 74ALVT162821 Datasheet HTML 9Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 12 page
background image
Philips Semiconductors
Product specification
74ALVT162821
2.5V/3.3V 20-bit bus-interface D-type flip-flop;
positive-edge trigger with 30
W termination resistors (3-State)
1998 Oct 02
4
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
55, 54, 52, 51, 49,
48, 47, 45, 44, 43,
42, 41, 40, 38, 37,
36, 34, 33, 31, 30
1D0 - 1D9
2D0 - 2D9
Data inputs
2, 3, 5, 6, 8, 9, 10,
12, 13, 14,
15, 16, 17, 19, 20,
21, 23, 24, 26, 27
1Q0 - 1Q9
2Q0 - 2Q9
Data outputs
1, 28
1OE, 2OE
Output enable inputs
(active-Low)
56, 29
1CP, 2CP
Clock pulse inputs
(active rising edge)
4, 11, 18, 25, 32,
39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
VCC
Positive supply
voltage
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUTS
OPERATING
nOE
nCP
nDx
INTERNAL
REGISTER
nQ0 - nQ9
OPERATING
MODE
L
L
l
h
L
H
L
H
Load and read
register
L
X
NC
NC
Hold
H
H
X
Dn
NC
Dn
Z
Z
Disable
outputs
H = High voltage level
h
= High voltage level one set-up time prior to the Low-to-High
clock transition
L
= Low voltage level
l
= Low voltage level one set-up time prior to the Low-to-High
clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low to High clock transition
↑ = Not a Low-to-High clock transition
LOGIC DIAGRAM
CP Q
D
nD0
nQ0
nCP
nOE
CP Q
D
nD1
nQ1
CP Q
D
nD2
nQ2
CP Q
D
nD3
nQ3
CP Q
D
nD4
nQ4
CP Q
D
nD5
nQ5
CP Q
D
nD6
nQ6
CP Q
D
nD7
nQ7
CP Q
D
nD8
nQ8
CP Q
D
nD9
nQ9
SH00004



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com