24LC00ISLASHSN datasheet(6/34 Pages) MICROCHIP

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24AA00/24LC00/24C00

DS20001178J-page 6

 1996-2018 Microchip Technology Inc.

4.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the

SDA line during the Acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse.

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an Acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the slave must leave the data line high to enable

the master to generate the Stop condition (Figure 4-2).

FIGURE 4-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 4-2:

ACKNOWLEDGE TIMING

Note:

The 24XX00 does not generate any

Acknowledge bits if an internal program-

ming cycle is in progress.

(A)

(B)

(C)

(D)

(A)

(C)

SCL

SDA

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

SCL

Transmitter must release the SDA line at this point

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line at this point

so the Transmitter can continue sending data.

Data from transmitter

SDA

Acknowledge

Bit

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