Philips Semiconductors

Product specification

74ALVT16821

2.5V/3.3V 20-bit bus-interface D-type flip-flop;

positive-edge trigger (3-State)

2

1998 Feb 13

853-1869 18962

FEATURES

and 200V per Machine Model

resistors to hold unused inputs

DESCRIPTION

The 74ALVT16821 high-performance BiCMOS device combines

low static and dynamic power dissipation with high speed and high

compatibility to 5V.

The 74ALVT16821 has two 10-bit, edge triggered registers, with

each register coupled to a 3-State output buffer. The two sections of

each register are controlled independently by the clock (nCP) and

Output Enable (nOE) control gates.

Each register is fully edge triggered. The state of each D input, one

set-up time before the Low-to-High clock transition, is transferred to

the corresponding flip-flop’s Q output.

The 3-State output buffers are designed to drive heavily loaded

3-State buses, MOS memories, or MOS microprocessors.

The active Low Output Enable (nOE) controls all ten 3-State buffers

independent of the register operation. When nOE is Low, the data in

the register appears at the outputs. When nOE is High, the outputs

are in high impedance “off” state, which means they will neither drive

nor load the bus.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

SYMBOL

PARAMETER

2.5V

3.3V

UNIT

Propagation delay

nCP to nQ

2.6

2.7

1.7

1.8

ns

Input capacitance

3

3

pF

Output capacitance

9

9

pF

Total supply current

Outputs disabled

40

70

µA

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

56-Pin Plastic SSOP Type III

–40

°C to +85°C

74ALVT16821 DL

AV16821 DL

SOT371-1

56-Pin Plastic TSSOP Type II

–40

°C to +85°C

74ALVT16821 DGG

AV16821 DGG

SOT364-1