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74ALVT16952 数据表(PDF) 2 Page - NXP Semiconductors

部件名 74ALVT16952
功能描述  2.5V/3.3V ALVT 16-bit registered transceiver 3-State
PDF  14 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

74ALVT16952 数据表(HTML) 2 Page - NXP Semiconductors

  74ALVT16952 Datasheet HTML 1Page - NXP Semiconductors 74ALVT16952 Datasheet HTML 2Page - NXP Semiconductors 74ALVT16952 Datasheet HTML 3Page - NXP Semiconductors 74ALVT16952 Datasheet HTML 4Page - NXP Semiconductors 74ALVT16952 Datasheet HTML 5Page - NXP Semiconductors 74ALVT16952 Datasheet HTML 6Page - NXP Semiconductors 74ALVT16952 Datasheet HTML 7Page - NXP Semiconductors 74ALVT16952 Datasheet HTML 8Page - NXP Semiconductors 74ALVT16952 Datasheet HTML 9Page - NXP Semiconductors Next Button
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Philips Semiconductors
Product specification
74ALVT16952
2.5V/3.3V 16-bit registered transceiver (3-State)
2
1998 Mar 19
853-2053 19136
FEATURES
Two 8-bit registered transceivers
5V I/O Compatible
3-State buffers
Output capability: +64mA/–32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
Power-up 3-State
Power-up reset
No bus current loading when output is tied to 5V bus
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ALVT16952 is a high-performance BiCMOS product
designed for VCC operation at 2.5V or 3.3V with I/O compatibility up
to 5V.
The 74ALVT16952 is a dual octal registered transceiver. Two 8-bit
registers store data flowing in both directions between two
bidirectional buses. Data applied to the inputs is entered and stored
on the rising edge of the Clock (nCPXX) provided that the Clock
Enable (nCEXX) is Low. The data is then present at the 3-State
output buffers, but is only accessible when the Output Enable
(nOEXX) is Low. Data flow from A inputs to B outputs is the same as
for B inputs to A outputs.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
SYMBOL
PARAMETER
Tamb = 25°C; GND = 0V
2.5V
3.3V
UNIT
tPLH
tPHL
Propagation delay
nCPBA to nAx or
nCPAB to nBx
CL = 50pF;
3.0
3.0
2.3
2.3
ns
CIN
Input capacitance
VI = 0V or VCC
3
3
pF
CI/O
I/O pin capacitance
VI/O = 0V or VCC
Outputs disabled
9
9
pF
ICCZ
Total supply current
Outputs disabled
40
70
µA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°C to +85°C
74ALVT16952 DL
AV16952 DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°C to +85°C
74ALVT16952 DGG
AV16952 DGG
SOT364-1
LOGIC SYMBOL (IEEE/IEC)
C6
C5
C6
C5
1
56
54
3
5
6
8
9
10
12
13
14
52
51
49
48
47
45
44
43
1, 4, 5
55
2, 3, 6
2
EN4
EN3
EN2
EN1
1, 4, 5
2, 3, 6
EN4
EN3
EN2
EN1
15
16
17
19
20
21
23
24
26
31
29
28
27
30
42
41
40
38
37
36
34
33
SH00069



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