Philips Semiconductors

Product specification

74F322

8-bit serial/parallel register with sign extend (3-State)

1988 Apr 22

2

LOGIC SYMBOL

3

17

4

16

5

15

6

14

7

13

19

1

2

18

11

8

Q7

D0

D1

I/O0

I/O2

I/O4

I/O6

I/O1

I/O3

I/O5

I/O7

S

RE

S/P

CP

OE

SE

VCC = Pin 20

GND = Pin 10

12

SF00875

9

MR

LOGIC SYMBOL (IEEE/IEC)

SF00876

2EN15

C6/1

→

9

R

18

16

5

15

6

14

1

11

12

SRG8

G4

8

2

8, 4, 1, 6D

19

2, 6D

12, 13

7

13

Z7

Z14

G3

3M1[SHIFT]

3M2[PAR LOAD]

2, 96D

8, 15

Z8

G5

8, 5, 1, 6D

8, 4, 1, 6D

2, 6D

7, 15

4

3

17

FUNCTION TABLE

INPUTS

INPUTS

OPERATING

MODE

MR

RE

S/P

SE

S

OE*

CP

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

Q7

OPERATING

MODE

L

L

H

X

X

H

X

X

X

X

L

L

X

X

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

Clear

H

L

L

X

X

X

↑

I0

I1

I2

I3

I4

I5

I6

I7

I7

Parallel load

H

H

L

L

H

H

H

H

L

H

L

L

↑

↑

D0

D1

O0

O0

O1

O1

O2

O2

O3

O3

O4

O4

O5

O5

O6

O6

O6

O6

Shift right

H

L

H

L

X

L

↑

O0

O0

O1

O2

O3

O4

O5

O6

O6

Sign extend

H

H

X

X

X

L

X

NC

NC

NC

NC

NC

NC

NC

NC

NC

Hold

X

X

L

X

L

X

X

X

X

X

X

H

X

↑

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

NC

NC

3-State

*

= When the input is High, all I/O terminals are at the high impedance state, sequential operation or clearing of the register is not

affected.

H

= High voltage level

L

= Low voltage level

NC

= No change

X

= Don’t care

Z

= High impedance “off” state

↑

= Low-to-High clock transition

I0–I7

= The level of the steady state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q7) are

isolated from the I/O terminal.

D0–D7 = The level of the steady state inputs to the serial multiplexer input.

O0–O7 = The level of the respective Qn flip-flop prior to the last clock Low-to-High transition.

↑

= Not a Low-to-High clock transition