The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Ltd. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks

of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information

will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document.

STATS ChipPAC reserves the right to change the information at any time and without notice.

©Copyright 2005. STATS ChipPAC Ltd. All rights reserved.

January 2005

Corporate Office

10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823

Global Offices

USA 510-979-8000

JAPAN 81-43-351-3320

CHINA 86-21-5976-5858

MALAYSIA 603-4257-6222

KOREA 82-31-639-8911

TAIWAN 886-3-593-6565

UK 44-1483-413-700

NETHERLANDS 31-38-333-2023

TQFP

Thin Profile Quad Flat Pack

PACKAGE CONFIGURATIONS

Package Size (mm)

Lead Count

7 x 7

32, 48

10 x 10

44, 52, 64

12 x 12

80, 100

14 x 14

100, 128

SPECIFICATIONS

Die Thickness

230-280

µm (9-11mils) range preferred

Gold Wire

25/30

µm (1.0/1.2mils) diameter, 99.999%Au

Lead Finish

85/15 Sn/Pb or Matte Tin

Marking

Laser/ink

Packing Options

JEDEC tray/tape and reel

RELIABILITY

Moisture Sensitivity Level

JEDEC Level 3

Temperature Cycling

-65°C/150°C, 1000 cycles

High Temperature Storage

150°C, 500 hrs

Pressure Cooker Test

121°C 100% RH,

2 atm, 168 hrs

Liquid Thermal Shock (opt)

-55°C/125°C, 1000 cycles

THERMAL PERFORMANCE,

θθθθθja (°C/W)

Package

Body Size (mm)

Pad Size (mm)

Die Size (mm)

Thermal Performance,

θθθθθja (°C/W)

48L

7 x 7 x 1.0

5.3 x 5.3

3.8 x 3.8

53.4

100L

14 x 14 x 1.0

9.0 x 9.0

7.8 x 7.8

38.6

Note: Simulation data for package mounted on 4 layer PCB (per JEDEC JESD51-7) under natural convection as defined in JESD51-2.

CROSS-SECTION

ELECTRICAL PERFORMANCE

Electrical parasitic data is highly dependent on the package layout. 3D electrical simulation can be used on the specific package design

to provide the best prediction of electrical behavior. Data below is for a frequency of 100MHz and assumes 1.0 mil gold bonding wire.

Conductor

Length

Resistance

Inductance

Inductance

Capacitance

Capacitance

Component

(mm)

(mOhms)

(nH)

Mutual (nH)

(pF)

Mutual (pF)

Wire

2

120

1.65

0.45 - 0.85

0.10

0.01 - 0.02

Lead (7 x 7mm, 32L)

1.4 - 2.2

11.0 - 18.0

0.64 - 0.99

0.31 - 0.49

0.21 - 0.33

0.07 - 0.12

Total (7 x 7mm, 32L)

131 - 138

2.29 - 2.64

0.76 - 1.34

0.31 - 0.43

0.08 - 0.14

Wire

2

120

1.65

0.45 - 0.85

0.10

0.01 - 0.02

Lead (14 x 14mm, 128L)

3.0 - 4.5

24.0 - 36.0

1.96 - 2.92

1.08 - 1.61

0.45 - 0.67

0.20 - 0.30

Total (14 x 14mm, 128L)

144.0 - 156.0

3.61 - 4.57

1.53 - 2.46

0.55 - 0.77

0.21 - 0.32