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74F621 数据表(PDF) 2 Page - NXP Semiconductors

部件名 74F621
功能描述  Octal bus transceiver, non-inverting open collector
PDF  10 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

74F621 数据表(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74F621
Octal bus transceiver, non-inverting (open collector)
2
1996 Jan 05
853–0380 16185
FEATURES
High-impedance NPN base inputs for reduced loading
(20
µA in High and Low states)
Octal bidirectional bus interface
Open collector outputs sink 64mA
Non-inverting
DESCRIPTION
The 74F621 is an octal transceiver featuring non-inverting open
collector bus-compatible outputs in both send and receive
directions. The outputs are capable of sinking 64mA, providing very
good capacitive drive characteristics.
This octal bus transceiver is designed for asynchronous two-way
communication between data buses. The control function
implementation allows for maximum flexibility in timing.
The device allows data transmission from the A bus to the B bus or
from the B bus to the A bus, depending upon the logic levels at the
Enable inputs (OEBA and OEAB). The Enable inputs can be used to
disable the device so that the buses are effectively isolated.
The dual-enable configuration gives the 74F621 the capability to
store data by the simultaneous enabling of OEBA and OEAB. Each
output reinforces its input in this transceiver configuration. Thus,
when both control inputs are enabled and all other data sources to
the two sets of the bus lines are at high impedance, both sets of bus
lines (16 in all) will remain in their last states.
PIN CONFIGURATION
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
VCC
B1
B2
B3
B4
B5
B6
B7
OEAB
A1
A2
A3
A4
A5
A6
A7
GND
OEBA
A0
B0
SF01135
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY CURRENT
(TOTAL)
74F621
8.0ns
105mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG
DWG #
20-pin plastic DIP
N74F621N
SOT146-1
20-pin plastic SOL
N74F621D
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 - A7, B0 - B7
Data inputs
1.0/0.033
20
µA/20µA
OEBA, OEAB
Output Enable inputs
1.0/0.033
20
µA/20µA
A0 - A7
Data outputs
OC/40
OC/24mA
B0 - B7
Data outputs
OC/106.7
OC/64mA
NOTE: One (1.0) FAST unit load is defined as: 20
µA in the High state and 0.6mA in the Low state. OC = Open Collector.



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