Application information

VIPER26K

22/28

DS12978 Rev 1

5.1

Layout guidelines and design recommendations

A proper printed circuit board layout ensures the correct operation of any switch-mode

converter and this is also true for the VIPer. The main reasons to have a proper PCB layout

are:

 Provides clean signals to the IC, ensuring good immunity against external and switching

noises.

 Reduces the electromagnetic interferences, both radiated and conducted, to pass the

EMC tests more easily.

If the VIPer is used to design an SMPS, the following basic rules should be considered:

 Separate signal from power tracks. Generally, traces carrying signal currents should

run far from others carrying pulsed currents or with fast swinging voltages. Signal ground

traces should be connected to the IC signal ground, GND, using a single “star point”,

placed close to the IC. Power ground traces should be connected to the IC power ground,

GND. The compensation network should be connected to the COMP, maintaining the

trace to GND as short as possible. In the case of two-layer PCB, it is good practice to route

signal traces on one PCB side and power traces on the other side.

 Filter sensitive pins. Some crucial points of the circuit need or may need filtering. A small

high-frequency bypass capacitor to GND might be useful to get a clean bias voltage for

the signal part of the IC and protect the IC itself during EFT/ESD tests. A low ESL ceramic

capacitor (a few hundreds pF up to 0.1 μF) should be connected across VCC and GND,

placed as close as possible to the IC. With flyback topologies, when the auxiliary winding

is used, it is suggested to connect the VCC capacitor on the auxiliary return and then to

the main GND using a single track.

 Keep power loops as confined as possible. The area circumscribed by current loops

where high pulsed current flow should be minimized to reduce its parasitic self-inductance

and the radiated electromagnetic field. As a consequence, the electromagnetic

interferences produced by the power supply during the switching are highly reduced. In a

flyback converter the most critical loops are: the one including the input bulk capacitor, the

power switch, the power transformer, the one including the snubber, the one including the

secondary winding, the output rectifier and the output capacitor. In a buck converter the

most critical loop is the one including the input bulk capacitor, the power switch, the power

inductor, the output capacitor and the freewheeling diode.

 Reduce line lengths. Any wire acts as an antenna. With the very short rise times

exhibited by EFT pulses, any antenna can receive high voltage spikes. By reducing line

lengths, the level of received radiated energy is reduced, and the resulting spikes from

electrostatic discharges are lower. This also keeps both resistive and inductive effects to

a minimum. In particular, all traces carrying high currents, especially if pulsed (tracks of

the power loops) should be as short and wide as possible.

 Optimize track routing. As levels of pickup from static discharges are likely greater near

the edges of the board, it is wise to keep any sensitive lines away from these areas. Input

and output lines often need to reach the PCB edge at some stage, but they can be routed

away from the edge as soon as possible where applicable. Since vias are to be

considered inductive elements, it is recommended to minimize their number in the signal

path and avoid them in the power path.

 Improve thermal dissipation. An adequate copper area has to be provided under the

DRAIN pins as heatsink, while it is not recommended to place large copper areas on the

GND.