DS11873 Rev 5

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VIPer11

General description

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5.8

Direct feedback

The IC embeds a transconductance type error amplifier (E/A) whose inverting input and

output are FB and COMP, respectively. The internal reference voltage of the E/A is VFB_REF

(1.2 V typical value referred to GND). In non-isolated topologies, positive output voltages

are tightly set through a simple voltage divider applied to the output voltage terminal, FB and

GND.

The E/A output is scaled down and fed into the PWM comparator, where it is compared with

the voltage across the sense resistor in series to the sense-FET, thus setting the cycle-by-

cycle drain current limitation.

An R-C network connected across COMP (the output of the E/A) and GND pins is usually

used to stabilize the overall control loop.

The FB is provided with an internal pull-up to prevent a wrong IC behavior when the pin is

accidentally left floating.

The E/A is disabled if the FB voltage is lower than VFB_DIS (200 mV, typ.).

5.9

Secondary feedback

When a secondary feedback is required, the internal E/A has to be disabled shorting FB to

GND (VFB < VFB_DIS). With this setting, COMP is internally connected to a pre-regulated

voltage through the pull-up resistor RCOMP(DYN) and the voltage across COMP is set by the

current sunk.

This allows the output voltage value to be set through an external error amplifier (TL431 or

similar) placed on the secondary side, whose error signal is used to set the DRAIN peak

current setpoint corresponding to the output power demand. If isolation is required, the error

signal must be transferred through an optocoupler, with the phototransistor collector

connected across COMP and GND.

5.10

Pulse frequency modulation

If the output load is decreased, the feedback loop reacts lowering the VCOMP voltage, which

reduces the DRAIN peak current setpoint, down to the minimum value of IDLIM_PFM when

the VCOMPL threshold is reached.

If the load is furtherly decreased, the DRAIN peak current value is maintained at IDLIM_PFM

and some PWM cycles are skipped. This kind of operation is referred to as “pulse frequency

modulation” (PFM), the number of the skipped cycles depends on the balance between the

output power demand and the power transferred from the input. The result is an equivalent

switching frequency which can go down to some hundreds Hz, thus reducing all the

frequency-related losses.

This kind of operation, together with the extremely low IC quiescent current, allows very low

input power consumption in no-load and light load, while the low DRAIN peak current

value, IDLIM_PFM, prevents any audible noise which could arise from low switching

frequency values. When the load is increased, VCOMP increases and PFM is exited. VCOMP

reaches its maximum at VCOMPH and corresponding to that value, the DRAIN current

limitation (IDLIM) is reached.