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EM6607 数据表(PDF) 24 Page - EM Microelectronic - MARIN SA |
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EM6607 数据表(HTML) 24 Page - EM Microelectronic - MARIN SA |
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24 / 47 page ![]() R EM6607 Copyright © 2005, EM Microelectronic-Marin SA 24 www.emmicroelectronic.com Table 37. Register - CIRQD Bit Name Reset R/W Description 3 - 0 R/W Reserved, must written to 0 2 - 0 R/W* Reserved, must written to 0 1 DebCK 0 R/W Debouncer clock select (0=2ms : 1=16ms) 0 INTEN 0 R/W Enable interrupt to CPU (1=enabled) Figure 13. Interrupt Request generation IRQ mask bit which can be written to 0 or 1 (1 to enable an interrupt) interrupt request flag which is set on the input rising edge. Timer IRQ flag INTTE and prescaler IRQ flag INTPR arrive independent of their mask bits not to loose any timing information. But the μprocessor will be interrupted only with mask set to 1. |
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