Connection Diagrams

8 Lead PSOP Package (MRA)

8 Lead LLP Surface Mount Package (SD)

20161330

Top View

See NS Package Number MRA08A

20161350

Top View

See NS Package Number SDC08A

Ordering Information

TABLE 1. Package Marking and Ordering Information

Output Voltage

Grade

Order Information

Supplied as:

1.00

STD

LP3879MR-1.0

95 Units per Rail

1.00

STD

LP3879MRX-1.0

2500 Units on Tape and Reel

1.00

STD

LP3879SD-1.0

1000 Units on Tape and Reel

1.00

STD

LP3879SDX-1.0

4500 Units on Tape and Reel

1.20

STD

LP3879MR-1.2

95 Units per Rail

1.20

STD

LP3879MRX-1.2

2500 Units on Tape and Reel

1.20

STD

LP3879SD-1.2

1000 Units on Tape and Reel

1.20

STD

LP3879SDX-1.2

4500 Units on Tape and Reel

Pin Descriptions

Pin

Name

Function

1

BYPASS

The capacitor connected between BYPASS and GROUND lowers

output noise voltage level and is required for loop stability.

2

N/C

DO NOT CONNECT. This pin is used for post package test and must

be left floating.

3

GROUND

Device ground.

4

INPUT

Input source voltage.

5

OUTPUT

Regulated output voltage.

6

SENSE

Remote Sense. Tie directly to output or remotely at point of load for

best regulation.

7

N/C

No internal connection.

8

SHUTDOWN

Output is enabled above turn-on threshold voltage. Pull down to turn off

regulator output.

PSOP, LLP

DAP

SUBSTRATE

GROUND

The exposed die attach pad should be connected to a thermal pad at

ground potential. For additional information on using National

Semiconductor’s Non Pull Back LLP package, please refer to LLP

application note AN-1187

www.national.com

2