Rev. 1.3 September 2022

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AOZ9510QI

Detailed Description

The AOZ9510QI is an integrated half-bridge gate driver

for motor drive applications. The device includes one

half-bridge gate driver, capable of driving high-side and

low-side N-channel MOSFETs. The AOZ9510QI provides

adjustable source/sink current of both high/low-side gate

drive output current which can optimize performances of

EMI and efficiency on different PCB layout and

applications.

In addition, the AOZ9510QI provides several fault

protections, such as UVLO, OTP and non-overlapping

mechanism.

The AOZ9510QI is available in 23-pin 4mm×4mm QFN

package.

Input Power Architecture

The AOZ9510QI integrates an internal linear regulator to

generate 8V (2.5%) VCC from input pins. If input voltage

is lower than 5.2V, the linear regulator will be triggered

VB-VOUT UVLO. The VCC maximum source current is

1mA. Therefore, extra external source is needed when

operation switching frequency exceeds 30kHz.

Non-overlapping

For forbidding shoot-through, HIN or LIN is invalid when

HIN or LIN goes high state before other one. For

example, low-side gate state keeps low regardless of the

state of LIN when HIN is high at first, and vice versa.

Thermal Monitor

The junction temperature can be monitored by using

internal current mirror pass through internal diodes. The

related VTP equation can be approximated as below,

Adjustable Source/Sink Current

It's hard to meet all of EMI specifications in different

applications.

So,

AOZ9510QI

provides

external

adjustable resistors for tuning gate drive source and sink

current.

DSV1 and DVS2 are used to tune gate drive source and

sink current, respectively. A resistor connects between

each DVS pin and GND to setting gate drive source /sink

current by internal current mirror, as illustrated Figure 11.

Source and sink current use maximum capability to drive

when DVS pins are floating or the voltage on DVS pins

exceed 4V. User can get the same source and sink

capability by using DVS1 to design and DVS2 floating.

The suggestion range of RDVS is 20kΩ~100kΩ.

Figure 11. Source / Sink Current Setting

In addition, source and sink current controls are

implemented only during MOSFET Miller effect and VGS

>1V, as illustrated Figure 12.

Figure 12. Source/Sink Current Implement Waveform

mV

C

Temp

V

V

o

TP

6

)

25

(

9

.

1









DVS

1V

Sink

Source

1:2000:2000

DVS

DVS

R

V

I

1



RDVS

VGS

IHO/ILO

1V

Miller Effect

Setting by

DVS Pins