1998 Jun 10

4

Philips Semiconductors

Product specification

Dual JK flip-flop with set and reset;

negative-edge trigger

74HC/HCT112

Fig.4 Functional diagram.

FUNCTION TABLE

Note

be unpredictable.

H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP

transition

L = LOW voltage level

l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP

transition

q = lower case letters indicate the state of the referenced output one set-up

time prior to the HIGH-to-LOW CP transition

X = don’t care

↓ = HIGH-to-LOW CP transition

OPERATING MODE

INPUTS

OUTPUTS

nCP

nJ

nK

nQ

nQ

asynchronous set

L

H

X

X

X

H

L

asynchronous reset

H

L

X

X

X

L

H

undetermined

L

L

X

X

X

H

L

toggle

H

H

↓

hh

qq

load “0” (reset)

H

H

↓

lh

L

H

load “1” (set)

H

H

↓

hl

H

L

hold “no change”

H

H

↓

ll

q

q

Fig.5 Logic diagram (one flip-flop).