M34D64

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SUMMARY DESCRIPTION

These

electrically

erasable

programmable memory (EEPROM) devices are

organized as 8192 x 8.

Figure 2. Logic Diagram

memory protocol. This is a two wire serial interface

that uses a bi-directional data bus and serial clock.

The devices carry a built-in 4-bit Device Type

bus definition.

with all memory operations synchronized by the

serial clock. Read and Write operations are

initiated by a Start condition, generated by the bus

master. The Start condition is followed by a Device

Select Code and RW bit (as described in Table 2),

terminated by an acknowledge bit.

When writing data to the memory, the device

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master acknowledges the receipt of the data byte

in the same way. Data transfers are terminated by

a Stop condition after an Ack for Write, and after a

NoAck for Read.

Table 1. Signal Names

In order to prevent data corruption and inadvertent

Write operations during Power-up, a Power On

Reset (POR) circuit is included. The internal reset

threshold value, and all operations are disabled –

the device will not respond to any command. In the

voltage, below the POR threshold value, all

operations are disabled and the device will not

must be applied before applying any logic signal.

Figure 3. SO and TSSOP Connections

Note: 1. See page 17 (onwards) for package dimensions, and how

to identify pin-1.

AI02850B

3

E0-E2

SDA

VCC

M34D64

WC

SCL

VSS

E0, E1, E2

Chip Enable

SDA

Serial Data

SCL

Serial Clock

WC

Write Control

Supply Voltage

Ground

SDA

VSS

SCL

WC

E1

E0

VCC

E2

AI02851C

M34D64

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2

3

4

8

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