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M34D64-R 数据表(PDF) 15 Page - STMicroelectronics |
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M34D64-R 数据表(HTML) 15 Page - STMicroelectronics |
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15 / 21 page ![]() 15/21 M34D64 Table 14. AC Characteristics (M34D64-R) Note: 1. For a reSTART condition, or following a Write cycle. 2. Sampled only, not 100% tested. 3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. Test conditions specified in Table 9 and Table 8 Symbol Alt. Parameter Min. Max. Unit fC fSCL Clock Frequency 400 kHz tCHCL tHIGH Clock Pulse Width High 600 ns tCLCH tLOW Clock Pulse Width Low 1300 ns tDL1DL2 2 tF SDA Fall Time 20 300 ns tDXCX tSU:DAT Data In Set Up Time 100 ns tCLDX tHD:DAT Data In Hold Time 0 ns tCLQX tDH Data Out Hold Time 200 ns tCLQV 3 tAA Clock Low to Next Data Valid (Access Time) 200 900 ns tCHDX 1 tSU:STA Start Condition Set Up Time 600 ns tDLCL tHD:STA Start Condition Hold Time 600 ns tCHDH tSU:STO Stop Condition Set Up Time 600 ns tDHDL tBUF Time between Stop Condition and Next Start Condition 1300 ns tW tWR Write Time 10 ms |
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