5.1

Guidelines

•

Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-in for each input. To

avoid input signal oscillation, the wiring of each input should be as short as possible, and the use of RC

filters (R1, C1) on each input signal is suggested. The filters should be with a time constant of about 100 ns

and placed as close as possible to the IPM input pins.

•

The use of a bypass capacitor CVCC (aluminum or tantalum) can reduce the transient circuit demand on the

power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, a

decoupling capacitor C2 (100 to 220 nF, with low ESR and low ESL) should be placed as close as possible

to the Vcc pin and in parallel with the bypass capacitor.

•

The use of an RC filter (RSF, CSF) is recommended to prevent protection circuit malfunction. The time

constant (RSF x CSF) should be set to 1 μs and the filter must be placed as close as possible to the CIN pin.

•

The SD is an input/output pin (open-drain type if it is used as output). The capacitor CSD of the filter on SD

should be fixed no higher than 3.3 nF in order to assure the SD activation time τA ≤ 500 ns. Besides, the

filter should be placed as close as possible to the SD pin.

•

The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each

Cboot, filters high-frequency disturbance. Both Cboot and C3 (if present) should be placed as close as

possible to the U, V, W and Vboot pins. Bootstrap negative electrodes should be connected to U, V, W

terminals directly and separated from the main output wires.

•

To avoid overvoltage on the Vcc pin, a Zener diode (Dz1) can be used. Similarly on the Vboot pin, a Zener

diode (Dz2) can be placed in parallel with each Cboot.

•

The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in parallel with the

electrolytic capacitor Cvdc is useful to prevent surge destruction. Both capacitors C4 and Cvdc should be

placed as close as possible to the IPM (C4 has priority over Cvdc).

•

By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals

without an opto-couplers is possible.

•

Low-inductance shunt resistors have to be used for phase leg current sensing.

•

In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND should be as short as

possible.

•

The connection of SGN_GND to PWR_GND on one point only (close to the shunt resistor terminal) can

reduce the impact of power ground fluctuation.

These guidelines ensure the specifications of the device for application designs. For further details, please refer to

the relevant application note.

Table 14. Recommended operating conditions

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

VPN

Supply voltage

Applied between P-Nu, Nv, Nw

300

400

V

VCC

Control supply voltage

Applied between VCC-GND

13.5

15

18

V

VBS

High-side bias voltage

Applied between VBOOTi-OUTi

for i = U, V, W

13

18

V

tdead

Blanking time to prevent arm-short

For each input signal

1

µs

fPWM

PWM input signal

-40 °C < TC < 100 °C

-40 °C < TJ < 125 °C

25

kHz

TC

Case operation temperature

100

°C

STIPN2M50-H

Guidelines

DS11935 - Rev 6

page 13/19