Rev. 2.0 August 2022

www.aosmd.com

Page 8 of 13

AOZ9530QV

ALPHA & OMEGA

SEMIC ONDUCT OR

Detailed Description

The AOZ9530QV is an integrated half-bridge gate driver

for motor drive applications. The device includes one

half-bridge gate driver, capable of driving high-side and

low-side N-channel MOSFETs. The AOZ9530QV provides

adjustable source/sink current of both high/low-side gate

drive output current which can optimize performances of

EMI and efficiency on different PCB layout and applications.

In addition, the AOZ9530QV provides several fault

protections, such as OCP, UVLO, SCP, OTP and

non-overlapping mechanism.

The AOZ9530QV is available in 18-pin 3mm×3mm QFN

package.

Input Power Architecture

The AOZ9530QV integrates an internal linear regulator to

generate 8V (±3%) VCC from input pins. If input voltage

is lower than 5.1V, the linear regulator will be triggered

VB-VOUT UVLO. The VCC maximum source current is

1mA. Therefore, extra external source is needed when

operation switching frequency exceeds 30kHz.

Non-overlapping

For forbidding shoot-through, HIN or LIN is invalid when

HIN or LIN goes high state before other one. For example,

low-side gate state keeps low regardless of the state of LIN

when HIN is high at first, and vice versa.

So when shoot-through occurs, VOUT will follow the previous

normal state, as illustrated Figure 12.

HIN

LIN

VO

Shoot-through

Correct state

Figure 12. Shoot-through Behavior

Fault Protection

Over Current Protection (OCP)

There are fixed OCP/SCP points on AOZ9530QV

IOCP=14A and ISCP=28A.

The time point of OCP detection is 1μs (debounce time)

after the rising edge of HIN. If the current exceeds the IOCP,

the internal counter will start counting, as illustrated Figure

13. When 14 consecutive OCPs are detected, the high side

MOSFET will be turned off on the 14th time and the low side

MOSFET is turned on. This behavior is called current limit.

When the current is less than 0.8*IOCP, the current limit is

released.

1

2

3

13

14

12

HIN

LIN

VO

I

1us

I_OCP

0.8*I_OCP

Counter

De-bounce time

Current limit release

Figure 13. OCP timing diagram

Short Current Protection (SCP)

If the current is greater than SCP point, AOZ9530QV enters

SCP, VTP pin will be pulled high, and then AOZ9530QV

enters latch, VCC needs to be reset to return to normal

operation state.

Over Temperature Protection (OTP)

When the junction temperature reach 140°C, AOZ9530QV

enters OTP, and release when the temperature drops to

120°C.

Adjustable Source/Sink Current

It's hard to meet all of EMI specifications in different

applications. So, AOZ9530QV provides external adjustable

resistors for tuning gate drive source and sink current.

DVS is used to tune gate drive source and sink current,

respectively. A resistor connects between DVS pin and GND

to setting gate drive source/sink current by internal current

mirror, as illustrated Figure 14. Source and sink current use

maximum capability to drive when DVS pin is floating or the

voltage on DVS pin exceed 4V. The suggestion range of

RDVS is 20kΩ~100kΩ.

DVS

1V

Sink

Source

1:2000:2000

DVS

DVS

R

V

I

1

=

RDVS

Figure 14. Source/Sink Current Setting