74HC174DB datasheet(2/13 Pages) PHILIPS

2 / 13 page

1998 Jul 08

Philips Semiconductors

Product speciﬁcation

Hex D-type ﬂip-ﬂop with reset; positive-edge trigger

74HC/HCT174

FEATURES

• Six edge-triggered D-type flip-flops

• Asynchronous master reset

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT174 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT174 have six edge-triggered D-type

flip-flops with individual D inputs and Q outputs. The

common clock (CP) and master reset (MR) inputs load and

reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D

input, one set-up time prior to the LOW-to-HIGH clock

transition, is transferred to the corresponding output of the

flip-flop.

A LOW level on the MR input forces all outputs LOW,

independently of clock or data inputs.

The device is useful for applications requiring true outputs

only and clock and master reset inputs that are common to

all storage elements.

QUICK REFERENCE DATA

GND = 0 V; Tamb=25 °C; tr =tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/ tPLH

propagation delay

CL = 15 pF; VCC =5 V

CP to Qn

MR to Qn

fmax

maximum clock frequency

MHz

input capacitance

3.5

CPD

power dissipation

capacitance per flip-flop

notes 1 and 2

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