74HCT393D datasheet(2/7 Pages) PHILIPS

2 / 7 page

December 1990

Philips Semiconductors

Product speciﬁcation

Dual 4-bit binary ripple counter

74HC/HCT393

FEATURES

• Two 4-bit binary counters with individual clocks

• Divide-by any binary module up to 28 in one package

• Two master resets to clear each 4-bit counter

individually

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT393 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT393 are 4-bit binary ripple counters with

separate clocks (1CP and 2 CP) and master reset (1MR

and 2MR) inputs to each counter. The operation of each

half of the “393” is the same as the “93” except no external

clock connections are required.

The counters are triggered by a HIGH-to-LOW transition of

the clock inputs. The counter outputs are internally

connected to provide clock inputs to succeeding stages.

The outputs of the ripple counter do not change

synchronously and should not be used for high-speed

address decoding.

The master resets are active-HIGH asynchronous inputs

to each 4-bit counter identified by the “1” and “2” in the pin

description.

A HIGH level on the nMR input overrides the clock and

sets the outputs LOW.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/ tPLH

propagation delay

CL = 15 pF; VCC = 5 V

nCP to nQ0

nQ to nQn+1

nMR to nQn

fmax

maximum clock frequency

MHz

input capacitance

3.5

CPD

power dissipation capacitance per counter

notes 1 and 2

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