Application Information

EXTERNAL CAPACITORS

To assure regulator stability, input and output capacitors are

required as shown in the Typical Application Circuit.

Output Capacitor

A minimum output capacitance of 10 µF, ceramic, is required

for stability. The amount of output capacitance can be in-

creased without limit. The output capacitor must be located

less than 1 cm from the output pin of the IC and returned to

the device ground pin with a clean analog ground.

Only high quality ceramic types such as X5R or X7R should

be used, as the Z5U and Y5F types do not provide sufficient

capacitance over temperature.

Tantalum capacitors will also provide stable operation across

the entire operating temperature range. However, the effects

of ESR may provide variations in the output voltage during

fast load transients. Using the minimum recommended 10

µF ceramic capacitor at the output will allow unlimited ca-

pacitance, Tantalum and/or Aluminum, to be added in paral-

lel.

Input Capacitor

The input capacitor must be at least 10 µF, but can be

increased without limit. It’s purpose is to provide a low

source impedance for the regulator input. A ceramic capaci-

tor, X5R or X7R, is recommended.

Tantalum capacitors may also be used at the input pin. There

is no specific ESR limitation on the input capacitor (the lower,

the better).

Aluminum electrolytic capacitors can be used, but are not

recommended as their ESR increases very quickly at cold

temperatures. They are not recommended for any applica-

tion where the ambient temperature falls below 0˚C.

Bias Capacitor

The capacitor on the bias pin must be at least 1 µF, and can

be any good quality capacitor (ceramic is recommended).

INPUT VOLTAGE

The input voltage (V

rail that will be regulated down to a lower voltage, which is

applied to the load. The input voltage must be at least V

OUT

+V

BIAS VOLTAGE

The bias voltage (V

required to bias the control circuitry and provide gate drive

for the N-FET pass transistor. The bias voltage must be in

the range of 3.0V to 5.5V to ensure proper operation of the

device.

UNDER VOLTAGE LOCKOUT

The bias voltage is monitored by a circuit which prevents the

device from functioning when the bias voltage is below the

Under-Voltage Lock-Out (UVLO) threshold of approximately

2.45V.

As the bias voltage rises above the UVLO threshold the

device control circuitry becomes active. There is approxi-

mately 150 mV of hysteresis built into the UVLO threshold to

provide noise immunity.

When the bias voltage is between the UVLO threshold and

the Minimum Operating Rating value of 3.0V the device will

be functional, but the operating parameters will not be within

the guaranteed limits.

SUPPLY SEQUENCING

There is no requirement for the order that V

applied or removed.

One practical limitation is that the Soft-Start circuit starts

charging C

the application of V

efits of Soft-Start will be compromised.

In any case, the output voltage cannot be guaranteed until

both V

operating values.

If used in a dual-supply system where the regulator output

load is returned to a negative supply, the output pin must be

diode clamped to ground. A Schottky diode is recommended

for this diode clamp.

REVERSE VOLTAGE

A reverse voltage condition will exist when the voltage at the

output pin is higher than the voltage at the input pin. Typically

this will happen when V

continues to hold a sufficient charge such that the input to

output voltage becomes reversed.

The NMOS pass element, by design, contains no body

diode. This means that, as long as the gate of the pass

element is not driven, there will not be any reverse current

flow through the pass element during a reverse voltage

event. The gate of the pass element is not driven when V

BIAS

is below the UVLO threshold.

When V

cuitry is active and will attempt to regulate the output voltage.

Since the input voltage is less than the output voltage the

control circuit will drive the gate of the pass element to the

full V

this condition, reverse current will flow from the output pin to

the input pin , limited only by the R

and the output to input voltage differential. This condition is

outside the guaranteed operating range and should be

avoided.

SOFT-START

The LP38859 incorporates a Soft-Start function that reduces

the start-up current surge into the output capacitor (C

allowing V

plished by controlling V

timing capacitor (C

rises above the Under-Voltage Lock-Out threshold (ULVO).

V

of the SS pin (r

the SS pin. This allows the output voltage to rise in a con-

trolled manner until steady-state regulation is achieved. Typi-

cally, five time constants are recommended to assure that

the output voltage is sufficiently close to the final steady-

state value. During the soft-start time the output current can

rise to the built-in current limit.

Soft-Start Time = C

(1)

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