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5CSEBA6U19C8ES 数据表(PDF) 7 Page - Intel Corporation |
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5CSEBA6U19C8ES 数据表(HTML) 7 Page - Intel Corporation |
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7 / 37 page ![]() Related Information True LVDS Buffers in Devices, I/O Features in Cyclone V Devices Provides the number of LVDS channels in each device package. Package Plan Table 5. Package Plan for Cyclone V E Devices Member Code M383 (13 mm) M484 (15 mm) U324 (15 mm) F256 (17 mm) U484 (19 mm) F484 (23 mm) F672 (27 mm) F896 (31 mm) GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO A2 223 — 176 128 224 224 — — A4 223 — 176 128 224 224 — — A5 175 — — — 224 240 — — A7 — 240 — — 240 240 336 480 A9 — — — — 240 224 336 480 Cyclone V GX This section provides the available options, maximum resource counts, and package plan for the Cyclone V GX devices. The information in this section is correct at the time of publication. For the latest information and to get more details, refer to the Product Selector Guide. Related Information Product Selector Guide Provides the latest information about Intel products. Cyclone V Device Overview 683694 | 2018.05.07 Send Feedback Cyclone V Device Overview 7 |
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